Configuration Modes and Pins
Virtex®-5 devices are configured by loading application-specific configuration data—the bitstream—into internal memory. Because Xilinx FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is loaded into the device through special configuration pins. These configuration pins serve as the interface for a number of different configuration modes:
Master-serial configuration modeSlave-serial configuration mode
Master SelectMAP (parallel) configuration mode (x8 and x16 only)Slave SelectMAP (parallel) configuration mode (x8, x16, and x32)JTAG/Boundary-Scan configuration mode
Master Serial Peripheral Interface (SPI) Flash configuration modeMaster Byte Peripheral Interface Up (BPI-Up) Flash configuration mode(x8 and x16 only)
Master Byte Peripheral Interface Down (BPI-Down) Flash configuration mode(x8 and x16 only)
The configuration modes are explained in detail in Chapter2, “Configuration Interfaces.” The specific configuration mode is selected by setting the appropriate level on the dedicated Mode input pins M[2:0]. The M2, M1, and M0 mode pins should be set at a constant DC voltage level, either through pull-up or pull-down resistors, or tied directly to ground or VCC_CONFIG. The mode pins should not be toggled during and after configuration. See Table2-1, page37 for the mode pin setting options.
The terms Master and Slave refer to the direction of the configuration clock (CCLK):
In Master configuration modes, the Virtex-5 device drives CCLK from an internaloscillator. To get the desired frequency, BitGen -g ConfigRate is used. The“BitGen” section of the Development System Reference Guide provides more
information. After configuration, the CCLK is turned off unless the persist optionis selected or SEU detection is used. The CCLK pin is 3-stated with a weak pull-up.In Slave configuration modes, CCLK is an input.
The JTAG/Boundary-Scan configuration interface is always available, regardless of the Mode pin settings. The JTAG/Boundary-Scan configuration mode disables all other configuration modes to prevent conflicts between configuration interfaces.
Certain pins are dedicated to configuration (Table1-1), while others are dual-purpose (Table1-2). Dual-purpose pins serve both as configuration pins and as user I/O after configuration. Dedicated configuration pins retain their function after configuration.
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
7.8.9.
On some Xilinx PROMs, the reset polarity is programmable. Reset should beconfigured as active Low when using this setup.
The Xilinx PROM must be set for parallel mode. This mode is not available for alldevices.
When configuring a Virtex-5 device in SelectMAP mode from a Xilinx configurationPROM, the RDWR_B and CS_B signals can be tied Low (see “SelectMAP DataLoading”).
10.The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page73.11.Ganged SelectMap configuration is specific to the Platform Flash XCFS and XCFP
PROM only.If one device is designated as the Master, the DONE pins of all devices must be connected with the active DONE drivers disabled. An external pull-up resistor is required on the common DONE signal. Designers must carefully focus on signal integrity due to the increased fanout of the outputs from the PROM. Signal integrity simulation is recommended.
Readback is not possible if the CS_B signals are tied together, because all devices simultaneously attempt to drive the D signals.
SelectMAP Data Loading
The SelectMAP interface allows for either continuous or non-continuous data loading. Data loading is controlled by the CS_B, RDWR_B, CCLK, and BUSY signals.
CS_B
The Chip Select input (CS_B) enables the SelectMAP bus. When CS_B is High, the Virtex-5 device ignores the SelectMAP interface, neither registering any inputs nor driving any outputs. D and BUSY are placed in a High-Z state, and RDWR_B is ignored.
If CS_B = 0, the device's SelectMAP interface is enabled.If CS_B = 1, the device's SelectMAP interface is disabled.
For a multiple device SelectMAP configuration, refer to Figure2-12.
If only one device is being configure through the SelectMAP and readback is not required, or if ganged SelectMAP configuration is used, the CS_B signal can be tied to ground, as illustrated in Figure2-9 and Figure2-13.
RDWR_B
RDWR_B is an input to the Virtex-5 device that controls whether the data pins are inputs or outputs:
If RDWR_B = 0, the data pins are inputs (writing to the FPGA).If RDWR_B = 1, the data pins are outputs (reading from the FPGA).
For configuration, RDWR_B must be set for write control (RDWR_B=0). For readback, RDWR_B must be set for read control (RDWR_B=1) while CS_B is deasserted. (For details, refer to Chapter7, “Readback and Configuration Verification.”)
Changing the value of RDWR_B while CS_B is asserted triggers an ABORT if the device gets a rising CCLK edge (see “SelectMAP ABORT”). If readback is not needed, RDWR_B can be tied to ground or used for debugging with SelectMAP ABORT.
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
Chapter 2:Configuration Interfaces
Virtex-5 FPGA Configuration Guide
UG191 (v3.13) July 28, 2020
SPI Configuration Interface
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
Byte Peripheral Interface Parallel Flash Mode
Power-On Sequence Precautions
At power-on, the FPGA automatically starts its configuration procedure. When the FPGA is in a Master-BPI configuration mode, the FPGA asserts FCS_B Low and drives a sequence of addresses to read the bitstream from a BPI Flash. The BPI Flash must be ready for asynchronous reads before the FPGA drives FCS_B Low and outputs the first address to ensure the BPI Flash can output the stored bitstream.
Because different power rails can supply the FPGA and BPI Flash or because the FPGA and BPI flash can respond at different times along the ramp of a shared power supply, special attention to the FPGA and BPI Flash power-on sequence or power-on ramps is essential. The power-on sequence or power supply ramps can cause the FPGA to awake before the BPI Flash or vice versa. For many systems with near-simultaneous power supply ramps, the FPGA power-on reset time (TPOR) can sufficiently delay the start of the FPGA configuration procedure such that the BPI Flash becomes ready before the start of the FPGA configuration procedure. In general, the system design must consider the effect of the power sequence, the power ramps, FPGA power-on reset time, and BPI Flash
power-on reset time on the timing relation between the start of FPGA configuration and the readiness of the BPI Flash for asynchronous reads. Check DS202, Virtex-5 FPGA Data Sheet: DC and Switching Characteristics data sheet for Virtex-5 FPGA power supply
requirements and timing. Check DS617, Platform Flash XL High-Density Configuration and Storage Device data sheet for the BPI Flash power supply requirements and timing.One of the following system design approaches can ensure that the BPI Flash is ready for asynchronous reads before the FPGA starts its configuration procedure:
Control the sequence of the power supplies such that the BPI Flash is certain to bepowered and ready for asynchronous reads before the FPGA begins its configurationprocedure.
Hold the FPGA PROGRAM_B pin Low from power-up to delay the start of the FPGAconfiguration procedure and release the PROGRAM_B pin to High after the BPI flashis fully powered and is able to perform asynchronous reads.
Hold the FPGA INIT_B pin Low from power-up to delay the start of the FPGAconfiguration procedure and release the INIT_B pin to High after the BPI flashbecomes ready for asynchronous reads.
See the Power-On Precautions if 3.3V Supply is Last in Sequence subsection of the Master BPI Mode section in UG332, Spartan-3 Generation Configuration User Guide, for reference.
Page Mode Support
Many NOR Flash devices support asynchronous page reads. The first access to a page usually takes the longest time (~100ns), subsequent accesses to the same page take less time (~25ns). The following parameters are bitstream programmable in Virtex-5 devices to take advantage of page reads and maximize the CCLK frequency:
Page sizes of 1 (default), 4, or 8.
If the actual Flash page size is larger then 8, the value of 8 should be used to maximizethe efficiency.
First access CCLK cycles of 1 (default), 2, 3, or 4. CCLK cycles must be 1 if the pagesize is 1.CCLK frequency
The sequence of page-mode operation is controlled by the Virtex-5 bitstream (see
Table6-15). After an FPGA reset, the default page size is 1, the first access CCLK is 1, and
Virtex-5 FPGA Configuration GuideUG191 (v3.13) July 28, 2020
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