专利内容由知识产权出版社提供
专利名称：Static timing analysis and dynamic simulation
for custom and ASIC designs
发明人：Mau-Chung Chang申请号：US11347029申请日：20060203
公开号：US20060200786A1公开日：20060907
专利附图：
摘要：A single verification tool provides both static timing analysis and timingsimulation capabilities targeted at both full-custom and ASIC designs in a unifiedenvironment. In various embodiments the verification tool includes the following
features: (a) Integrating both static timing analysis and dynamic simulation tools into asingle tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cyclecircuit in the presence of level sensitive latch, (c) Automatically identifying circuitstructure, e.g. complex gate, for timing characterization, (d) Circuit structures at
transistor level solved by incorporating function check, (e) Carrying out functional checkto filter out failing path and identifying gate with simultaneously changing inputs, (f)Finding maximum operation frequency in the presence of level sensitive latches afterfiltering out false paths, (g) Crosstalk solver by utilizing the admittance matrix andvoltage transfer of RLC part in frequency domain coupled with the non-linear driver intime domain implemented in spice-like simulator, (h) Making use of the correlationbetween inputs of aggressors and victim to determine switching time at victim's outputiteratively.
申请人：Mau-Chung Chang
地址：Hillsborough CA US
国籍：US
更多信息请下载全文后查看