HD74LS156
Dual 2-line-to-4-line Decoders / Demultiplexers (with open collector outputs)
REJ03D0441–0300
Rev.3.00 Jul.13.2005
This circuit features dual 1-line-to-4-line demultiprexer with individual strobes and common binary-address input. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route
associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating.
Features
• Ordering Information
Part Name
Package Type
Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DG-A (FP-16DNV)
Package
Abbreviation
Taping Abbreviation (Quantity)
HD74LS156P DILP-16 pin HD74LS156RPEL
SOP-16 pin (JEDEC)
P — FP
EL (2,500 pcs/reel)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
Data 1CStrobe 1GSelect Input B1Y3Outputs1Y21Y11Y0GND123456781Y31G1C1Y21Y11Y0BBAA2G2Y32CBBAA2Y22Y12Y0161514131211109VCCData 2CStrobe 2GSelect Input A2Y32Y2Outputs2Y12Y0(Top view)
Rev.3.00, Jul.13.2005, page 1 of 6
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HD74LS156
Function Table
• 2-to-4-line Decoder / 1-to-4-line Demultiplexer
Inputs Outputs Select Strobe Data 1Y0 1Y1 1Y2 1Y3
B A 1G 1C X X H X H H H H L L L H L H H H L H L H H L H H H L L H H H L H H H L H H H H L X X X L H H H H
Inputs Outputs Select Strobe Data 2Y0 2Y1 2Y2 2Y3
B A 2G 2C X X H X H H H H L L L L L H H H L H L L H L H H H L L L H H L H H H L L H H H L X X X H H H H H
• 3-to-8-line Decoder / 1-to-8-line Demultiplexer
Strobe or
(0) (1) (2) (3) (4) (5) (6) (7) Data
C*1 B A G*2 2Y0 2Y1 2Y2 2Y3 1Y0 1Y1 1Y2 1Y3
X X X H H H H H H H H H L L L L L H H H H H H H L L H L H L H H H H H H L H L L H H L H H H H H L H H L H H H L H H H H H L L L H H H H L H H H H L H L H H H H H L H H H H L L H H H H H H L H H H H L H H H H H H H L Notes: 1. C; input 1C and 2C connected together
2. G; inputs 1G and 2G connected together 3. H; high level, L; low level, X; irrelevant
Select
Inputs Outputs Rev.3.00, Jul.13.2005, page 2 of 6
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HD74LS156
Block Diagram
Strobe1GData1CSelectB1Y01Y11Y21Y32Y0SelectAData2CStrobe2G2Y12Y22Y3Outputs
Absolute Maximum Ratings
Supply voltage Input voltage Power dissipation Storage temperature
VCC VIN PT Tstg
Item Symbol Ratings Unit 7 V 400 mW –65 to +150
°C
7 V Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Supply voltage
High level output voltage Low level output current Operating temperature
VCC VOH IOL Topr
4.75 5.00 5.25 V — — 5.5 V — — 8 mA –20 25 75 °C
Item Symbol Min Typ Max Unit Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Input voltage Output current Output voltage
Symbol min. typ.* max. Unit VIH 2.0 — — V VIL — — 0.8 V IOH — — 100 µA VOL
Condition
— — 0.4 V
— — 0.5 IIH — — 20 µA VCC = 5.25 V, VI = 2.7 V
Input current IIL — — –0.4 mA VCC = 5.25 V, VI = 0.4 V
— 0.1 mA VCC = 5.25 V, VI = 7 V II — Supply current** ICC — 6.1 10 mA VCC = 5.25 V Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA Notes: * VCC = 5 V, Ta = 25°C ** ICC is measured with outputs open, A, B, and 1C inputs at 4.5 V, and 2C, 1G, and 2G inputs grounded.
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, VOH = 5.5V
IOL = 4 mA VCC = 4.75 V, VIH = 2 V, IOL = 8 mA VIL = 0.8 V
Rev.3.00, Jul.13.2005, page 3 of 6
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HD74LS156
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Level of
Item Symbol Inputs Output logic
tPLH tPHL
A, B, 2C, 1G or 2G
min. typ. max. Unit Condition Y 2 — 25 40 Propagation
delay time
A, B, 2C,
Y 2 — 34 51 1G or 2G
ns
tPLH A or B Y 3 — 31 46 tPHL A or B Y 3 — 34 51 tPLH 1C Y 3 — 32 48 Y 3 — 32 48 tPHL 1C CL = 15 pF,
RL = 2 kΩ
Testing Method
Test Circuit
VCC4.5V1Y0InputP.G.Zout = 50ΩRL1G1CBA2C2G1Y11Y21Y32Y02Y12Y22Y3CLOutputSee Testing Table Note: CL includes probe and jig capacitance.
Rev.3.00, Jul.13.2005, page 4 of 6
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HD74LS156 Waveform
tTLH90%1.3 VtPLHtTHL90%1.3 V3 V10%tPHL0 VVOHIn phase outputtPHL1.3 VtPLH1.3 VVOLInput10%VOHOut of phase output1.3 V1.3 VVOL Note: Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50%
Rev.3.00, Jul.13.2005, page 5 of 6
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HD74LS156
Package Dimensions
JEITA Package CodeP-DIP16-6.3x19.2-2.54RENESAS CodePRDP0016AE-BPrevious CodeDP-16FVMASS[Typ.]1.05gD16910.b 38ZEAReferenceSymbolDimension in MillimetersMinNom7.6219.26.320.327.45.060.510.400.481.300.190°2.292.540.250.3115°2.791.122.540.56MaxA 1eDEAL1A1eb pbp3θe1cbcθeZ( Ni/Pd/Au plating )L
JEITA Package CodeP-SOP16-3.95x9.9-1.27RENESAS CodePRSP0016DG-APrevious CodeFP-16DNVMASS[Typ.]0.15g*1D9F16NOTE)1. DIMENSIONS\"*1 (Nom)\"AND\"*2\"DO NOT INCLUDE MOLD FLASH.2. DIMENSION\"*3\"DOES NOTINCLUDE TRIM OFFSET.bpIndex mark*2EHEcReferenceSymbolDimension in MillimetersMinNom9.903.95Max10.30Terminal cross section ( Ni/Pd/Au plating )1Ze*3DEA28b pxML1A1Abpb1cc10.100.140.251.750.340.400.460.150.200.25θHE0°5.806.101.278°6.20AθA 1Lyexy0.250.150.6350.401Detail FZLL0.601.081.27
Rev.3.00, Jul.13.2005, page 6 of 6
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