LTE Band41/38/xGP MIPI APT PA 2.0x2.5mm Power Amplifier Module
Preliminary Data Sheet
Features
Thin Package (0.9mm typ.)
Excellent Linearity in Average Power Tracking Mode MIPI RFFE Interface 2-mode power
10-pin surface mounting package
Internal 50ohm matching networks for both RF input and output Separate Drive and Output VCC Supplies Green - Lead-free and RoHS compliant
Applications
Band41 TD-LTE Band38 TD-LTE xGP
Ordering Information
Part Number
Number of Devices
Container BULK
ACPM-9341-BLK 100 ACPM-9341-TR1
1,000
178mm (7”) Tape/Reel
This preliminary data is provided to assist you in the evaluation of product(s) currently under development. Until Avago Technologies releases this product for general sales, Avago Technologies reserves the right to alter prices, specifications, features, capabilities, functions, release dates, and remove availability of the product(s) at anytime.
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Absolute Maximum Ratings
No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value Operation of any single parameter outside these conditions with the remaining parameters set at or below nominal values may result in permanent damage
Description Min. Typ. Max. Unit RF Input Power 0 10.0 dBm DC Supply Voltage 0 3.4 5.0 V Control Voltage 0 1.8 3.3 V
℃ Storage Temperature (Tstg) -55 25 +125
Recommended Operating Condition
Description Min. Typ. Max. Unit
DC Supply Voltage Vbat 3.2 3.4 4.5 V VCC1 & VCC2 0.5 3.4 3.5 Operating Frequency (fo) 2496 2690 MHz Ambient Temperature (Ta) -20 25 +90 Ԩ
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MIPI RFFE Interface
PA Slave Configuration Registers and Address Mapping
Reg Addr
Register Name
# of Bits
R/W
Default Value
BID Support
GSID Support
Trigger Support
Comments
Bits 6:3 – Reserved Bit 2 – PA Enable Bits 1:0 – PA Mode 01: HPM – APT 10: LPM – APT PA Bias Fixed Reserved
Bit 7 – Software reset
Bit 6 – Command Frame Parity Error
Bit 5 – Command Length Error Bit 4 – Address Frame Parity Error Bit 3 – Data Frame Parity Error Bit 2 – Read Unused Register Bit 1 – Write Unused Register Bit 0 – BID/GID Error
Bits 7:4 – Reserved (Reads 0x0) Bits 3:0 ‐ Group Slave ID Bits 7:6 – PWR_MODE
00: Normal Operation (ACTIVE) 01: (STARTUP)
10: Default (LOW POWER) 11: Reserved
Bit 5 – Trigger Mask 2 Bit 4 – Trigger Mask 1 Bit 3 – Trigger Mask 0 Bit 2 – Trigger 2 Bit 1 – Trigger 1 Bit 0 – Trigger 0
P ID bits 7:0 for B41 (0000 1010) Manufacturer ID lower byte Bits 7:6 – Spare (0x0)
Bits 5:4 – Manufacturer ID upper bits Bits 3:0 ‐ USID
0x00 Register 0
7
R/W 0x00 No No Yes
0x01 0x02‐0x19 Register 1 Register 2 – Register 19
8 ‐
R/W ‐
0x00 ‐
No ‐
No ‐
Yes ‐
0x1A RFFE_STATUS 8
R/W (See Note1)
0x00 No No No
0x1B GROUP_SID 8 R/W 0x00 No No No
0x1C PM_TRIG 8 R/W 0x80
Yes (See Note 2) Yes (See Note 2)
No
0x1D 0x1E
PRODUCT_ID MANUFACTURER_ID MAN_USID
8 8
R R
0x0A 0x07
No No
No No
No No
0x1F 6 R/W 0x1F No No No
Notes:
1. Read of the Status register will yield the current value and the content will be cleared on the completion of Read Command Sequence.
2. BID/GSID support for PM_TRIG register applies only to bits 7:6 (PWR_MODE) and bits 2:0 (Trigger 2‐0)
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PA Control Sequence
To be updated
Timing Specification
To be updated
Reference Documents
[1] MIPI® Alliance Specification for RF Front-End Control Interface, Version 1.01 Revision 0.04 – 26 July 2011
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Electrical Characteristics
- Conditions: VCC1/2=3.4V, T=25℃, Zin/Zout=50ohm
Characteristics Operating Frequency Range Maximum Output Power (High Power Mode) Gain (LTE MPR=0dB)
Mid Power Mode , Pout = 13.5dBm High Power Mode ,Pout=28.4dBm, LTE 10MHz 12RB MPR=0dB,VCC1/2=3.4V
Power Added Efficiency
High Power Mode ,Pout=28.4dBm, LTE 10MHz 12RB MPR=0dB, VCC1/2=3.2V
Mid Power Mode, Pout=13.5dBm, LTE 10MHz 12RB MPR=0dB, VCC1/2=2.1V
High Power Mode ,Pout=28.4dBm, LTE 10MHz 12RB MPR=0dB,VCC1/2=3.4V
Total Supply Current
High Power Mode ,Pout=28.4dBm, LTE 10MHz 12RB MPR=0dB, VCC1/2=3.2V
Mid Power Mode, Pout=13.5dBm, LTE 10MHz 12RB MPR=0dB, VCC1/2 =2.1V High Power Mode ,Pout=28.4dBm, LTE 10MHz12RB MPR=0dB, VCC1/2=3.4V; ɳdcdc=93%
Power Added Efficiency (APT)
(Overall PAE - Assumes ɳdcdc 80%- 93%)
High Power Mode ,Pout=28.4dBm, LTE 10MHz 12RB MPR=0dB, VCC1/2=3.2V ɳdcdc=93% Mid Power Mode, Pout=13.5dBm, LTE 10MHz 12RB MPR=0dB, VCC1/2=2.1V; ɳdcdc=80% High Power Mode ,Pout=28.4dBm, LTE 10MHz 12RB MPR=0dB, VCC1/2=3.2V; ɳdcdc=93%
Total Supply Current (APT)
(Overall PAE - Assumes ɳdcdc 80%- 93%)
High Power Mode ,Pout=28.4dBm, LTE 10MHz 12RB MPR=0dB, VCC1/2=3.2V; ɳdcdc=93% Mid Power Mode, Pout=13.5dBm, LTE 10MHz 12RB MPR=0dB, VCC1/2=2.1V; ɳdcdc=80%
Digital Control Signal Current (SCLK, SDATA) Total Current in Power-down mode Quiescent Current
Mid Power Mode
LTE
Adjacent Channel Leakage Ratio Harmonics
3fo
Stability (Spurious Output) VSWR 5:1, All phase E-UTRAACLR UTRAACLR1 UTRAACLR2 2fo High Power Mode, Pout=28.4dBm
TBD Pout < (maximum power –MPR) Pout < (maximum power –MPR) Pout < (maximum power –MPR)
TBD -38.1 -37.4 -47 TBD
dBc dBc
mA dBc dBc dBc dBc
High Power Mode
40.4 % 18 dB Condition LTE, MPR=0dB High Power Mode, Pout = 28.4dBm Min. 2496 Typ. – Max. 2690 Unit MHz 28.4 27 dBm dB 35 % 36.6 % 12.95 % 594 mA 606 mA 84 mA 36.2 % 18.7 % 576 mA 547 mA 56 mA
TBD
50 10
µA µA mA
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Input VSWR Rx Band Noise Power GPS Band Noise Power ISM Band Noise Power Ruggedness
10MHz LTE, +30MHz offset from Tx, average +/-4.5MHz , 20RB
High Power Mode, Pout=28.4dBm High Power Mode, Pout=28.4dBm Pout<28.4dBm, Pin<10dBm, All phase 2:1
TBD dBm/Hz
TBD TBD
dBm/Hz dBm/Hz
10:1
High Power Mode
LTE signal signal configuration used:
3GPP2 TDD-LTE Coexistence, Table 6.6.2.3.2.1 Note 2
TDD-LTE, 10MHz, 12RB, RB_start=0 MPR=0 Pout=28.4dBm TDD-LTE, 10MHz, 50RB, MPR=1 Pout=27.4dBm
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Footprint
All dimensions are in millimeter
X-Ray Top View
PIN Description
Pin #
Name
Description
DC Supply Voltage, connect 1st RF stage
1 VCC1
collector to which APT applied ( 0.5V~3.5V) 2 RFIN
RF Input
DC Supply Voltage, connect to bias circuitry
3 VBAT
with fix voltage (higher than 3.2V)
4 VIO RFFE Enable 5 SDATA 6 SCLK 7 GND 9 RFOUT
RFFE Data RFFE Clock Ground RF Output
8 NC No Connection DC Supply Voltage, connect to 2nd RF stage 10 VCC2
collector to which APT applied ( 0.5V~3.5V)
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Package Dimensions
All dimensions are in millimeter
Pin 1 Mark1098762.0 ± 0.1 0.9 ± 0.1 1 2 3 4 5 2.5 ± 0.1
Marking Specification
Pin 1 Mark ● EDZZ 9341 D – Date Code
ZZ – Assembly Lot Identification 9341 – Device Code
Note: Prior to production release, the marking will be ‘EDZZ’. After the completion of Avago qualification testing and production release, the marking will revert to ‘DZZ’, as shown above.
Date Code Table (Year & Month Code)
Year20112012201320142015201620172018201920202021JanV8lyLYbpBP2FebW9mzMZcqCQ3MacMar XanAN1drDR4AprYbpBP2esES5MayZcqCQ3ftFT6Jun1drDR4guGU7Jul2esES5hvHV8Aug3ftFT6jwJW9Sep4guGU7kxKXaOct5hvHV8lyLYbNov6jwJW9mzMZcDec7kxKXanAN1d
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Evaluation Board Schematic
Evaluation Board Description
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Metallization
Solder Mask Opening
Solder Paste Stencil Aperture
*Notes :
1. CPL_IN(ISO) line and RFout line are recommended to be at the different layer for better CPL_IN(ISO)/RFout isolation.
PCB Design Guidelines
The recommended PCB land pattern is shown in figures on the left side. The substrate is coated with solder mask between the I/O and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging.
Stencil Design Guidelines
A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. The recommended stencil layout is shown here. Reducing the stencil opening can potentially generate more voids. On the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the I/O pads or conductive paddle to adjacent I/O pads. Considering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use laser cut stencil composed of
0.100mm(4mils) or 0.127mm(5mils) thick stainless steel which is capable of producing the required fine stencil outline.
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10Handling and Storage
ESD (Electrostatic Discharge)
Electrostatic discharge occurs naturally in the environment. With the increase in voltage potential, the outlet of neutralization or discharge will be sought. If the acquired discharge route is through a semiconductor device, destructive damage will result. ESD countermeasure methods should be developed and used to control potential ESD damage during handling in a factory environment at each manufacturing site. MSL (Moisture Sensitivity Level)
Plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature.
Moisture Classification Level and Floor Life MSL Level 1
Avago Technologies follows JEDEC Standard J-STD 020B. Each component and package type is classified for moisture sensitivity by soaking a known dry package at various temperatures and relative humidity, and times. After soak, the components are subjected to three consecutive simulated reflows.
The out of bag exposure time maximum limits are determined by the classification test describe below which corresponds to a MSL classification level 6 to 1 according to the JEDEC standard IPC/JEDEC J-STD-020B and J-STD-033.
ACPM-9341 is MSL3. Thus, according to the J-STD-033 p.11 the maximum Manufacturers Exposure Time (MET) for this part is 168 hours. After this time period, the part would need to be removed from the reel, de-taped and then re-baked. MSL
classification reflow temperature for the ACPM-9341 is targeted at 260℃ +0/-5℃. Figure and table on next page show typical SMT profile for maximum temperature of 260 +0/-5℃.
Floor Life (out of bag) at factory ambient =< 30oC/60% RH or as stated Unlimited at =< 30oC/85% RH
2 1 year 2a 4 weeks 3
168 hours
4 72 hours 5 48 hours 5a 24 hours 6 Note :
1. The MSL Level is marked on the MSL Label on each shipping bag.
Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label
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Reflow Profile Recommendations
Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5Ԩ
Typical SMT Reflow Profile for Maximum Temperature = 260 +0/ -5ԨProfile Feature
Sn-Pb Solder Pb-Free Solder Average ramp-up rate (TL to TP) 3Ԩ/sec max 3Ԩ /sec max Preheat
- Temperature Min (Tsmin) 100Ԩ 150Ԩ - Temperature Max (Tsmax) 150Ԩ 200Ԩ - Time (min to max) (ts) 60-120 sec 60-180 sec Tsmax to TL
- Ramp-up Rate 3Ԩ /sec max Time maintained above: - Temperature (TL) 183Ԩ 217Ԩ - Time (TL) 60-150 sec
60-150 sec
Peak temperature (Tp) 240 +0/-5Ԩ 260 +0/-5Ԩ Time within 5Ԩ of actual Peak Temperature (tp) 10-30 sec 20-40 sec Ramp-down Rate
6Ԩ /sec max 6Ԩ /sec max Time 25Ԩ to Peak Temperature
6 min max.
8 min max.
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Storage Condition
Packages described in this document must be stored in sealed moisture barrier, antistatic bags. Shelf life in a sealed moisture barrier bag is 12 months at <40Ԩ and 90% relative humidity (RH) J-STD-033 p.7.
Out-of-Bag Time Duration
After unpacking the device must be soldered to the PCB within 168 hours as listed in the J-STD-020B p.11 with factory conditions <30Ԩ and 60% RH. Baking
It is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfied. Baking must be done if at least one of the conditions above have not been satisfied. The baking conditions are 125Ԩ for 12 hours J-STD-033 p.8. CAUTION
Tape and reel materials typically cannot be baked at the temperature described above. If out-of-bag exposure time is exceeded, parts must be baked for a longer time at low
temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (See moisture sensitive warning label on each shipping bag for information of baking).
Board Rework
Component Removal, Rework and Remount
If a component is to be removed from the board, it is
recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200Ԩ. This method will minimize moisture related component damage. If any component temperature exceeds 200Ԩ, the board must be baked dry per 4-2 prior to rework and/or component removal. Component temperatures shall be measured at the top center of the package body. Any SMD packages that have not exceeded their floor life can be exposed to a maximum body temperature as high as their specified maximum reflow temperature.
Removal for Failure Analysis
Not following the above requirements may cause moisture/reflow damage that could hinder or completely prevent the determination of the original failure mechanism. Baking of Populated Boards
Some SMD packages and board materials are not able to withstand long duration bakes at 125Ԩ. Examples of this are some FR-4 materials, which cannot withstand a 24 hr bake at 125Ԩ. Batteries and electrolytic capacitors are also temperature sensitive. With component and board temperature restrictions in mind, choose a bake temperature from Table 4-1 in J-STD 033; then determine the appropriate bake duration based on the component to be removed. For additional considerations see IPC-7711 andIPC-7721.
Derating due to Factory Environmental Conditions
Factory floor life exposures for SMD packages removed from the dry bags will be a function of the ambient environmental conditions. A safe, yet conservative, handling approach is to
expose the SMD packages only up to the maximum time limits for each moisture sensitivity level as shown in next table. This approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30Ԩ/60% RH. A solution for addressing this problem is to derate the
exposure times based on the knowledge of moisture diffusion in the component package materials ref. JESD22-A120). Recommended equivalent total floor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device.
Table on next page lists equivalent derated floor lives for
humidities ranging from 20-90% RH for three temperature, 20Ԩ, 25Ԩ, and 30Ԩ.
Table on next page is applicable to SMDs molded with novolac, biphenyl or multifunctional epoxy mold compounds. The following assumptions were used in calculating this table:
1. Activation Energy for diffusion = 0.35eV (smallest known value).
2. For ≤60% RH, use Diffusivity = 0.121exp ( -0.35eV/kT) mm2/s (this used smallest known Diffusivity @ 30Ԩ).
3. For >60% RH, use Diffusivity = 1.320exp ( -0.35eV/kT) mm2/s (this used largest known Diffusivity @ 30Ԩ).
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13Recommended Equivalent Total Floor Life (days) @ 20Ԩ, 25 Ԩ & 30 Ԩ, 35 Ԩ
For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was classified) Maximum Percent Relative Humidity
Maximum Percent Relative Humidity
Package Type and Body Thickness
Moisture Sensitivity
Level
5% ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞
10% 20% 30% 40% 50% 60% 70% 80% 90% ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 3 5 6 8 2 4 5 7 1 2 3 5 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 5 7 9 11 3 4 5 6 1 2 2 3 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 7 10 13 18
94 124 167 231 8 10 13 17 3 4 5 7 2 3 5 7 1 1 2 4 ∞ ∞ ∞ ∞ 12 19 25 32 4 5 7 9 2 3 4 5 1 1 2 2 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 7 13 18 26 2 3 5 6
44 60 78 103 7 9 11 14 3 4 5 7 2 3 4 6 1 1 2 3 ∞ ∞ ∞ ∞ 9 12 15 19 3 4 5 7 2 3 3 5 1 1 2 2 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 7 9 12 17 3 5 6 8 1 2 3 4
32 41 53 69 6 8 10 13 2 4 5 7 2 2 4 5 1 1 2 3 58 86 148 ∞ 7 9 12 15 3 4 5 6 2 2 3 4 1 1 2 2 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 4 5 7 9 2 3 4 6 1 1 2 3
26 33 42 57 6 7 9 12 2 3 5 7 1 2 3 5 1 1 2 3 30 39 51 69 6 8 10 13 2 3 4 6 2 2 3 4 1 1 2 2 ∞ ∞ ∞ ∞ 8 11 14 20 3 4 5 7 2 2 3 5 1 1 2 2
16 28 36 47 6 7 9 12 2 3 4 6 1 2 3 4 1 1 2 2 22 28 37 49 5 7 9 12 2 3 4 5 1 2 3 4 1 1 2 2 17 28 ∞ ∞ 5 7 10 13 2 3 4 6 1 2 3 4 1 1 2 2
7 10 14 19 4 5 7 10 2 3 3 5 1 2 2 3 1 1 1 2 3 4 6 8 2 3 5 7 1 2 3 4 1 1 2 3 1 1 1 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 1 2
5 7 10 13 3 4 6 8 1 2 3 4 1 1 2 3 1 1 1 2 2 3 4 5 2 2 3 5 1 2 2 3 1 1 1 3 0.5 0.5 1 2 0.5 1 1 2 0.5 1 1 2 0.5 1 1 2 0.5 1 1 2 0.5 1 1 2
4 6 8 10 3 4 5 7 1 2 3 4 1 1 2 3 1 1 1 2 1 2 3 4 1 2 3 4 1 1 2 3 1 1 1 2 0.5 0.5 1 1 0.5 1 1 1 0.5 1 1 1 0.5 1 1 1 0.5 1 1 1 0.5 0.5 1 1
35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ 35Ԩ 30Ԩ 25Ԩ 20Ԩ
Level 2a
Body Thickness ≥3.1 mm
Including PQFPs >84 pin, PLCCs (square) All MQFPs
or All BGAs ≥1 mm
Level 5 Level 4 Level 3
Level 5a
Level 2a
Body 2.1 mm ≤ Thickness <3.1 mm including PLCCs (rectangular)
18-32 pin SOICs (wide body) SOICs ≥20 pins, PQFPs ≤80 pins
Level 5a Level 5 Level 4 Level 3
Level 2a
Body Thickness <2.1 mm
including SOICs <18 pin All TQFPs, TSOPs
or
All BGAs <1 mm body
thickness
Level 5 Level 4 Level 3
Level 5a
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited. in the United States and other countries. Data subject to change. Copyright © 2012 Avago Technologies Limited. All rights reserved.
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