library ieee;
use ieee.std_logic_11.all; use ieee.std_logic_unsigned.all; entity mm13 is port ( clk load d q );
end ;
architecture df of mm13 is signal begin
data :std_logic_vector(12 downto 0);
:in std_logic;
:in std_logic; :in std_logic_vector(12 downto 0);
:buffer std_logic
process(clk) is
variable c1,c4,c5,c12 begin
if load='0' then data<=d;
:std_logic;
elsif clk'event and clk='1' then q <=data(0); c1 := q xor data(1); c4 := c1 xor data(4);
c5 := c5 xor data(4); c12 := c5 xor data(12);
data<=c12 & data(12 downto 1); end if ; end process;
end df ;