AD9850 datasheet 数据手册

FEATURES125 MHz Clock RateOn-Chip High Performance DAC and High SpeedComparatorDAC SFDR > 50 dB @ 40MHz AOUT32-Bit Frequency Tuning WordSimplified Control Interface:Parallel Byte or SerialLoading FormatPhase Modulation Capability+3.3 V or +5 V Single Supply OperationLow Power:380 mW @ 125 MHz (+5 V)155 mW @ 110 MHz (+3.3 V)Power-Down FunctionUltrasmall 28-Lead SSOP PackagingAPPLICATIONSFrequency/Phase–Agile Sine-Wave SynthesisClock Recovery and Locking Circuitry for DigitalCommunicationsDigitally Controlled ADC Encode GeneratorAgile Local Oscillator ApplicationsGENERAL DESCRIPTIONThe AD9850 is a highly integrated device that uses advancedDDS technology coupled with an internal high speed, highperformance, D/A converter and comparator, to form a com-plete digitally programmable frequency synthesizer and clockgenerator function. When referenced to an accurate clocksource, the AD9850 generates a spectrally pure, frequency/phase-programmable, analog output sine wave. This sine wavecan be used directly as a frequency source or converted to asquare wave for agile-clock generator applications. The AD9850’sinnovative high speed DDS core provides a 32-bit frequencytuning word, which results in an output tuning resolution of0.0291 Hz, for a 125 MHz reference clock input. TheAD9850’s circuit architecture allows the generation of outputfrequencies of up to one-half the reference clock frequency (or62.5 MHz), and the output frequency can be digitally changed(asynchronously) at a rate of up to 23 million new frequenciesper second. The device also provides fivebits of digitallycontrolled phase modulation, which enables phase shifting of itsoutput in increments of 180°, 90°, 45°, 22.5°, 11.25° and anyREV.E

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

CMOS, 125 MHzComplete DDS SynthesizerAD9850FUNCTIONAL BLOCK DIAGRAM+VSGNDREFDAC RSETCLOCK INHIGH SPEED10-BITMASTERDDSDACANALOGOUTRESET32-BITPHASETUNINGANDWORDCONTROLANALOGFREQUENCYWORDSINUPDATE/FREQUENCY/PHASEDATA REGISTERDATA REGISTERRESETCLOCK OUTCLOCK OUTWORD LOADCLOCKDATA INPUT REGISTERCOMPARATORSERIALLOADPARALLELAD9850LOAD1-BIT 40 LOADS8-BITS 5 LOADSFREQUENCY, PHASE, AND CONTROLDATA INPUTcombination thereof. The AD9850 also contains a high speedcomparator that can be configured to accept the (externally)filtered output of the DAC to generate a low jitter square waveoutput. This facilitates the device’s use as an agile clock gen-erator function.The frequency tuning, control, and phase modulation words areloaded into the AD9850 via a parallel byte or serial loadingformat. The parallel load format consists of five iterative loadsof an 8-bit control word (byte). The first byte controls phasemodulation, power-down enable, and loading format; bytes 2–5comprise the 32-bit frequency tuning word. Serial loading isaccomplished via a 40-bit serial data stream on a single pin. TheAD9850 Complete-DDS uses advanced CMOS technology toprovide this breakthrough level of functionality and performanceon just 155 mW of power dissipation (+3.3 V supply).The AD9850 is available in a space saving 28-lead SSOP, sur-face mount package. It is specified to operate over the extendedindustrial temperature range of –40°C to +85°C.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700World Wide Web Site: http://www.analog.comFax: 781/326-8703© Analog Devices, Inc., 1999

AD9850–SPECIFICATIONS(V = +5 V ؎ 5% except as noted, R

S

SET = 3.9 k⍀)

ParameterCLOCK INPUT CHARACTERISTICSFrequency Range+5 V Supply+3.3 V SupplyPulsewidth High/Low+5 V Supply+3.3 V SupplyDAC OUTPUT CHARACTERISTICSFull-Scale Output CurrentRSET = 3.9 kΩRSET = 1.95 kΩGain ErrorGain Temperature CoefficientOutput OffsetOutput Offset Temperature CoefficientDifferential NonlinearityIntegral NonlinearityOutput Slew Rate (50Ω, 2 pF Load)Output ImpedanceOutput CapacitanceVoltage ComplianceSpurious-Free Dynamic Range (SFDR):Wideband (Nyquist Bandwidth)1 MHz Analog Out20 MHz Analog Out40 MHz Analog OutNarrowband40.13579 MHz ± 50 kHz40.13579 MHz ± 200 kHz4.513579 MHz ± 50 kHz/20.5 MHz CLK4.513579 MHz ± 200 kHz/20.5 MHz CLKCOMPARATOR INPUT CHARACTERISTICSInput CapacitanceInput ResistanceInput CurrentInput Voltage RangeComparator Offset*COMPARATOR OUTPUT CHARACTERISTICSLogic “1” Voltage +5 V SupplyLogic “1” Voltage +3.3 V SupplyLogic “0” VoltagePropagation Delay, +5 V Supply (15 pF Load)Propagation Delay, +3.3 V Supply (15 pF Load)Rise/Fall Time, +5 V Supply (15 pF Load)Rise/Fall Time, +3.3 V Supply (15 pF Load)Output Jitter (p-p)CLOCK OUTPUT CHARACTERISTICSClock Output Duty Cycle (Clk Gen. Config.)TempTest LevelAD9850BRSMinTypMaxUnitsFullFull+25°C+25°CIVIVIVIV113.24.1125110MHzMHznsns+25°C+25°C+25°CFull+25°CFull+25°C+25°C+25°C+25°C+25°C+25°C+25°C+25°C+25°C+25°C+25°C+25°C+25°C+25°C+25°C+25°C+25°CFullFullFullFull+25°C+25°C+25°C+25°C+25°C+25°CVVIVIVIIVIVIVIIVIVIVIVIVIVIVVIVIIVVIVIVIVIVVVVVIV10.2420.48–1015010500.50.54001200.75181.5635046725854807784843500–12030+4.8+3.1+0.45.5733.58050 ± 10+12VDD30+1050mAmA% FSppm/°CµAnA/°CLSBLSBV/µskΩpFVdBcdBcdBcdBcdBcdBcdBcpFkΩµAVmVVVVnsnsnsnsps%–2–REV. E

AD9850

ParameterCMOS LOGIC INPUTS (Including CLKIN)Logic “1” Voltage, +5 V SupplyLogic “1” Voltage, +3.3 V SupplyLogic “0” VoltageLogic “1” CurrentLogic “0” CurrentInput CapacitancePOWER SUPPLY (AOUT = 1/3 CLKIN)+VS Current @:62.5 MHz Clock, +3.3 V Supply110 MHz Clock, +3.3 V Supply62.5 MHz Clock, +5 V Supply125 MHz Clock, +5 V SupplyPDISS @:62.5 MHz Clock, +3.3 V Supply110 MHz Clock, +3.3 V Supply62.5 MHz Clock, +5 V Supply125 MHz Clock, +5 V SupplyPDISS Power-Down Mode+5 V Supply+3.3 V SupplyNOTES*Tested by measuring output duty cycle variation.Specifications subject to change without notice.Temp+25°C+25°C+25°C+25°C+25°C+25°CTest LevelIIIIIVAD9850BRSMinTypMax3.53.00.412123UnitsVVVµAµApFFullFullFullFullFullFullFullFullFullFullVIVIVIVIVIVIVIVIVV304744761001552203803010486096160200320480mAmAmAmAmWmWmWmWmWmWTIMING CHARACTERISTICS*(V = +5 V ؎ 5% except as noted, R

S

SET = 3.9 k⍀)

ParametertDStDHtWHtWLtWDtCDtFHtFLtCFtFDtRHtRLtRStOLtRR(Data Setup Time)(Data Hold Time)(W_CLK min. Pulsewidth High)(W_CLK min. Pulsewidth Low)(W_CLK Delay After FQ_UD)(CLKIN Delay After FQ_UD)(FQ_UD High)(FQ_UD Low)(Output Latency from FQ_UD)Frequency ChangePhase Change(FQ_UD Min. Delay After W_CLK)(CLKIN Delay After RESET Rising Edge)(RESET Falling Edge After CLKIN)(Minimum RESET Width)(RESET Output Latency)(Recovery from RESET)Wake-Up Time from Power-Down ModeTempFullFullFullFullFullFullFullFullFullFullFullFullFullFullFullFull+25°CTest LevelIVIVIVIVIVIVIVIVIVIVIVIVIVIVIVIVVAD9850BRSMinTypMax3.53.53.53.57.03.57.07.018137.03.53.551325UnitsnsnsnsnsnsnsnsnsCLKIN CyclesCLKIN CyclesnsnsnsCLKIN CyclesCLKIN CyclesCLKIN CyclesµsNOTES*Control functions are asynchronous with CLKIN.Specifications subject to change without notice.REV. E–3–

AD9850

ABSOLUTE MAXIMUM RATINGS*EXPLANATION OF TEST LEVELSMaximum Junction Temperature . . . . . . . . . . . . . . . +165°CVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 VDigital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VSDigital Output Continuous Current . . . . . . . . . . . . . . . 5 mADAC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mAStorage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°COperating Temperature . . . . . . . . . . . . . . . . .–40°C to +85°CLead Temperature (Soldering 10 sec) . . . . . . . . . . . . +300°CSSOP θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 82°C/W*Absolute maximum ratings are limiting values, to be applied individually, andbeyond which the serviceability of the circuit may be impaired. Functionaloperability under any of these conditions is not necessarily implied. Exposure ofabsolute maximum rating conditions for extended periods of time may affectdevice reliability.Test LevelI–100% Production Tested.III–Sample Tested Only.IV–Parameter is guaranteed by design and characterizationtesting.V–Parameter is a typical value only.VI–All devices are 100% production tested at +25°C.100% production tested at temperature extremes formilitary temperature devices; guaranteed by design andcharacterization testing for industrial devices.CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readilyaccumulate on the human body and test equipment and can discharge without detection.Although the AD9850 features proprietary ESD protection circuitry, permanent damage mayoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.Application Note: Users are cautioned not to apply digital input signals prior to power-up of thisdevice. Doing so may result in a latch-up condition.WARNING!ESD SENSITIVE DEVICEORDERING GUIDEModelAD9850BRSTemperature Range–40°C to +85°CPackage DescriptionShrink Small Outline (SSOP)Package OptionRS-28–4–

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Table I.Lead Function DescriptionsPinNo.4–1,28–255, 246, 23710, 1911, 1812MnemonicD0–D7DGNDDVDDW_CLKFQ_UDCLKINAGNDAVDDRSETFunction8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and 8-bit phase/control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data word.Digital Ground. These are the ground return leads for the digital circuitry.Supply Voltage Leads for digital circuitry.Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words.Frequency Update. On the rising edge of this clock, the DDS will update to the frequency (or phase)loaded in the data input register, it then resets the pointer to Word 0.Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at1/2V supply. The rising edge of this clock initiates operation.Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator).Supply Voltage for the analog circuitry (DAC and comparator).This is the DAC’s external RSET connection. This resistor value sets the DAC full-scale output current. Fornormal applications (FS IOUT = 10 mA), the value for RSET is 3.9 kΩ connected to ground. The RSET/IOUTrelationship is: IOUT = 32 (1.248 V/RSET).Output Complement. This is the comparator’s complement output.Output True. This is the comparator’s true output.Inverting Voltage Input. This is the comparator’s negative input.Noninverting Voltage Input. This is the comparator’s positive input.1314151617202122QOUTBQOUTVINNVINPDACBL (NC)DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and shouldnormally be considered a “no connect” for optimum performance.IOUTBIOUTRESETThe Complementary Analog Output of the DAC.Analog Current Output of the DAC.Reset. This is the master reset function; when set high it clears all registers (except the input register) andthe DAC output will go to Cosine 0 after additional clock cycles—see Figure 19.PIN CONFIGURATIONSD3D2D1LSB D0DGNDDVDDWCLKFQUDCLKIN123456728D427D526D625D7 MSB/SERIAL LOAD24DGND23DVDD22RESETTOP VIEW8(Not to Scale)21IOUTAD9850920IOUTB19AGND18AVDD17DACBL (NC)16VINP15VINNAGND10AVDD11RSET12QOUTB13QOUT14NC = NO CONNECTREV. E

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AD9850–Typical Performance Characteristics

CH1SSpectrum10dB/REF–8.6dBm 76.2 dBAD9850CLOCK 125MHz Fxd0RBW # 100HzVBW 100HzATN # 30dBSWP 762 secSTART 0HzSTOP 62.5MHzFigure 1.SFDR, CLKIN = 125 MHz/fOUT = 1 MHzCH1SSpectrum10dB/REF–10dBm 54.818 dBAD9850CLOCK 125MHz Fxd0RBW # 300HzVBW 300HzATN # 30dBSWP 182.6 secSTART 0HzSTOP 62.5MHzFigure 2.SFDR, CLKIN = 125 MHz/fOUT = 41 MHzTek Run: 100GS/s ET Sample : 300ps @: 25.26ns1Ch 1 500mV⍀M 20.0ns Ch 1 1.58VD 500ps Runs AfterFigure 3.Typical Comparator Output Jitter, AD9850Configured as Clock Generator w/42 MHz LP Filter(40 MHz AOUT/125 MHz CLKIN)CH1SSpectrum10dB/REF–10dBm 59.925 dBAD9850CLOCK 125MHz Fxd0RBW # 300HzVBW 300HzATN # 30dBSWP 182.6 secSTART 0HzSTOP 62.5MHzFigure 4.SFDR, CLKIN = 125 MHz/fOUT = 20 MHzCH1SSpectrum12dB/REF0dBm–85.401 dBAD9850–23 kHzMkr0RBW # 3HzVBW 3HzATN # 20dBSWP 399.5 secCENTER 4.513579MHzSPAN 400kHzFigure 5.SFDR, CLKIN = 20.5 MHz/fOUT = 4.5 MHz–105 PN.3RD–110–115–120–125cBd–130–135–140–145–150–1551001k10k100kOFFSET FROM 5MHz CARRIER – HzFigure 6. Output Residual Phase Noise (5 MHz AOUT/125 MHz CLKIN)–6–

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Tek Run: 50.0GS/s ET Average Ch 1 Rise 2.870ns1Ch1 1.00V⍀ M 1.00ns Ch 1 1.74VFigure 7.Comparator Output Rise Time(5 V Supply/15 pF Load)68

fOUT = 1/3 OF CLKIN66

62Bd – R60DFS5856 VCC = 5V54 VCC = 3.3V52

0

20

40

6080100

120

140

CLKIN – MHz

Figure 8.SFDR vs. CLKIN Frequency(AOUT = 1/3 of CLKIN)9080A VCC = 5V m–70 TNERR60UC YLP50P VUCC = 3.3VS4030010203040FREQUENCY OUT – MHzFigure 9.Supply Current vs. AOUT Frequency(CLKIN = 125/110 MHz for 5 V/3.3 V Plot)REV. E

AD9850

Tek Run: 50.0GS/s ET Average Ch 1 Fall 3.202ns1Ch1 1.00V⍀ M 1.00ns Ch 1 1.74VFigure 10.Comparator Output Fall Time(5 V Supply/15 pF Load)9080A70m – TN60 VCC = 5VERRU50C YLP40PUS30 VCC = 3.3V2010020406080100120140CLOCK FREQUENCY – MHzFigure 11.Supply Current vs. CLKIN Frequency(AOUT = 1/3 of CLKIN)7570 fOUT = 1MHz65Bd – R60D FfOUT = 20MHzS55 fOUT = 40MHz50455101520DAC IOUT – mAFigure 12.SFDR vs. DAC IOUT (AOUT = 1/3 of CLKIN)–7–

AD9850

+VSGNDIOUT5-POLE ELLIPTICAL42MHz LOW-PASS200⍀ IMPEDANCELOW-PASSFILTERIFFREQUENCYINFILTER125MHzFILTERRFFREQUENCYOUT200⍀100k⍀8-b ؋ 5 PARALLEL DATA,OR 1-b ؋ 40 SERIAL DATA,DATA470pFPROCESSORBUSRESET, AND 2CLOCK LINES100k⍀100⍀IOUTBAD9850VINNXTALCLKVINPOSCQOUTCMOSQOUTBCLOCKOUTPUTSRSETCOMPCOMPLETE-DDSREFERENCEAD9850TUNINGWORDa.Frequency/Phase–Agile Local Oscillator200⍀125MHzREFERENCECLOCKTRUECOMPLETE-DDSTUNINGWORDAD9850FILTERPHASECOMPARATORDIVIDE-BY-NLOOPFILTERRFFREQUENCYOUTVCOFigure 13.Basic AD9850 Clock Generator Applicationwith Low-Pass Filterb.Frequency/Phase–Agile Reference for PLLREFFREQUENCYPHASECOMPARATORFILTERCOMPLETE-DDSLOOPFILTERVCORxIF INI8I/Q MIXERAD9059ANDDUAL 8-BIT8LOW-PASSQADCFILTERVCAADC CLOCKFREQUENCYLOCKED TO Tx CHIP/SYMBOL PN RATE125MHzREFERENCECLOCKDIGITALDEMODULATORRxBASEBANDDIGITALDATAOUTAGCRFFREQUENCYOUTADC ENCODEPROGRAMMABLE“DIVIDE-BY-N”FUNCTIONAD985032CLOCKGENERATORCHIP/SYMBOL/PNRATE DATAAD9850TUNING WORDc.Digitally-Programmable ”Divide-by-N“ Function in PLL Figure 15.AD9850 Complete-DDS Synthesizer in Frequency Up-Conversion ApplicationsFigure 14.AD9850 Clock Generator Application in aSpread-Spectrum ReceiverTHEORY OF OPERATION AND APPLICATIONThe AD9850 uses direct digital synthesis (DDS) technology, inthe form of a numerically controlled oscillator, to generate afrequency/phase-agile sine wave. The digital sine wave is con-verted to analog form via an internal 10-bit high speed D/Aconverter, and an onboard high speed comparator is provided totranslate the analog sine wave into a low jitter TTL/CMOS-compatible output square wave. DDS technology is an innova-tive circuit architecture that allows fast and precise manipulationof its output frequency under full digital control. DDS alsoenables very high resolution in the incremental selection ofoutput frequency; the AD9850 allows an output frequencyresolution of 0.0291 Hz with a 125 MHz reference clock ap-plied. The AD9850’s output waveform is phase-continuouswhen changed.The basic functional block diagram and signal flow of theAD9850 configured as a clock generator is shown in Figure 16.The DDS circuitry is basically a digital frequency divider functionwhose incremental resolution is determined by the frequency ofthe reference clock divided by the 2N number of bits in thetuning word. The phase accumulator is a variable-moduluscounter that increments the number stored in it each time itreceives a clock pulse. When the counter overflows it wrapsaround, making the phase accumulator’s output contiguous.The frequency tuning word sets the modulus of the counter thateffectively determines the size of the increment (∆ Phase) thatgets added to the value in the phase accumulator on the nextclock pulse. The larger the added increment, the faster the ac-cumulator overflows, which results in a higher output fre-quency. The AD9850 uses an innovative and proprietaryalgorithm that mathematically converts the 14-bit truncatedvalue of the phase accumulator to the appropriate COS value.This unique algorithm uses a much reduced ROM look-up tableand DSP techniques to perform this function, which contributesto the small size and low power dissipation of the AD9850. Therelationship of the output frequency, reference clock, and tuningword of the AD9850 is determined by the formula:fOUT = (∆ Phase × CLKIN)/232where:∆ Phase=value of 32-bit tuning wordCLKIN=input reference clock frequency in MHzfOUT=frequency of the output signal in MHzThe digital sine wave output of the DDS block drives the inter-nal high speed 10-bit D/A converter that reconstructs the sine–8–

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REFCLOCKDDS CIRCUITRYNPHASEACCUMULATORAMPLITUDE/COSCONV.ALGORITHMD/ACONVERTERLPCOMPARATORCLKOUTTUNING WORD SPECIFIESOUTPUT FREQUENCYAS A FRACTION OF REFCLOCK FREQUENCYIN DIGITAL DOMAINCOS (x)Figure 16.Basic DDS Block Diagram and Signal Flow of AD9850wave in analog form. This DAC has been optimized for dynamicperformance and low glitch energy as manifested in the lowjitter performance of the AD9850. Since the output of theAD9850 is a sampled signal, its output spectrum follows theNyquist sampling theorem. Specifically, its output spectrumcontains the fundamental plus aliased signals (images) thatoccur at multiples of the Reference Clock Frequency ± theselected output frequency. A graphical representation of thesampled spectrum, with aliased images, is shown in Figure 17.fOUTSIGNAL AMPLITUDEThe reference clock frequency of the AD9850 has a minimumlimitation of 1 MHz. The device has internal circuitry thatsenses when the minimum clock rate threshold has been exceededand automatically places itself in the power-down mode. Whenin this state, if the clock frequency again exceeds the threshold,the device resumes normal operation. This shutdown modeprevents excessive current leakage in the dynamic registers ofthe device.The D/A converter output and comparator inputs are availableas differential signals that can be flexibly configured in anymanner desired to achieve the objectives of the end-system. Thetypical application of the AD9850 is with single-ended output/input analog signals, a single low-pass filter, and generating thecomparator reference midpoint from the differential DAC out-put as shown in Figure 13.Programming the AD9850sin(x)/x ENVELOPE x=(pi)fo/fcfc–fofc+fofc2fc–fo2fc+fo3fc–fo120MHz20MHz80MHz2ND IMAGEFUNDAMENTAL1ST IMAGE100MHzREFERENCE CLOCKFREQUENCY180MHz3RD IMAGE220MHz4TH IMAGE280MHz5TH IMAGEThe AD9850 contains a 40-bit register that is used to program the32-bit frequency control word, the 5-bit phase modulation wordand the power-down function. This register can be loaded in aparallel or serial mode.In the parallel load mode, the register is loaded via an 8-bit bus;the full 40-bit word requires five iterations of the 8-bit word.The W_CLK and FQ_UD signals are used to address and loadthe registers. The rising edge of FQ_UD loads the (up to) 40-bitcontrol data word into the device and resets the address pointerto the first register. Subsequent W_CLK rising edges load the8-bit data on words [7:0] and move the pointer to the nextregister. After five loads, W_CLK edges are ignored until eithera reset or an FQ_UD rising edge resets the address pointer tothe first register.In serial load mode, subsequent rising edges of W_CLK shiftthe 1-bit data on Lead 25 (D7) through the 40 bits of program-ming information. After 40 bits are shifted through, an FQ_UDpulse is required to update the output frequency (or phase).The function assignments of the data and control words areshown in Table III; the detailed timing sequence for updatingthe output frequency and/or phase, resetting the device, andpowering-up/down, are shown in the timing diagrams of Figures18–24.Note:There are specific control codes, used for factory testpurposes, that render the AD9850 temporarily inoperable. Theuser must take deliberate precaution to avoid inputting thecodes listed in Table II.Figure 17. Output Spectrum of a Sampled SignalIn this example, the reference clock is 100 MHz and the outputfrequency is set to 20 MHz. As can be seen, the aliased imagesare very prominent and of a relatively high energy level as deter-mined by the sin(x)/x roll-off of the quantized D/A converteroutput. In fact, depending on the fo/Ref Clk relationship, thefirst aliased image can be on the order of –3dB below the fun-damental. A low-pass filter is generally placed between the out-put of the D/A converter and the input of the comparator tofurther suppress the effects of aliased images. Obviously, con-sideration must be given to the relationship of the selectedoutput frequency and the Reference Clock frequency to avoidunwanted (and unexpected) output anomalies.A good rule-of-thumb for applying the AD9850 as a clockgenerator is to limit the selected output frequency to <33% ofReference Clock frequency, thereby avoiding generating aliasedsignals that fall within, or close to, the output band of interest(generally dc-selected output frequency). This practice will easethe complexity (and cost) of the external filter requirement forthe clock generator application.REV. E

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Table II.Factory-Reserved Internal Test Control CodesLoading FormatParallelSerialFactory-Reserved Codes1) W0 = XXXXXX102) W0 = XXXXXX011) W32 = 1; W33 = 02) W32 = 0; W33 = 13) W32 = 1; W33 = 1tCDDATAW0*W1W2W3W4tDSWCLK tDHtWHtWLtFDtFLFQUDtFHREF CLK tCFCOS OUT*OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD AND IS ASYNCHRONOUS WITH THE REFERENCE CLOCKOLD FREQ (PHASE)VALID DATANEW FREQ (PHASE)SYMBOL DEFINITION MIN tDSDATA SETUP TIME3.5ns tDHDATA HOLD TIME3.5ns tWHWCLK HIGH3.5ns tWLWCLK LOW3.5ns tCDCLK DELAY AFTER FQ_UD3.5ns tFHFQUD HIGH7.0ns tFLFQUD LOW7.0ns tFDFQUD DELAY AFTER WCLK 7.0ns tCFOUTPUT LATENCY FROM FQUD FREQUENCY CHANGE18 CLOCK CYCLES PHASE CHANGE13 CLOCK CYCLESFigure 18.Parallel-Load Frequency/Phase Update Timing SequenceTable III.8-Bit Parallel-Load Data/Control Word Functional AssignmentWordW0W1W2W3W4data[7]Phase-b4(MSB)Freq-b31(MSB)Freq-b23Freq-b15Freq-b7data[6]Phase-b3Freq-b30Freq-b22Freq-b14Freq-b6data[5]Phase-b2Freq-b29Freq-b21Freq-b13Freq-b5data[4]Phase-b1Freq-b28Freq-b20Freq-b12Freq-b4data[3]Phase-b0 (LSB)Freq-b27Freq-b19Freq-b11Freq-b3data[2]Power-DownFreq-b26Freq-b18Freq-b10Freq-b2data[1]ControlFreq-b25Freq-b17Freq-b9Freq-b1data[0]ControlFreq-b24Freq-b16Freq-b8Freq-b0(LSB)–10–

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REF CLKtRHtRL tREV. E

RRRESET tRS tOLCOS OUTCOS (0)SYMBOL DEFINITION MIN SPEC tRHCLK DELAY AFTER RESET RISING EDGE3.5ns tRLRESET FALLING EDGE AFTER CLK3.5ns tRRRECOVERY FROM RESET2 CLK CYCLES tRSMINIMUM RESET WIDTH5 CLK CYCLES tOLRESET OUTPUT LATENCY13 CLK CYCLESRESULTS OF RESET:– FREQUENCY/PHASE REGISTER SET TO 0– ADDRESS POINTER RESET TO W0– POWER-DOWN BIT RESET TO “0”– DATA INPUT REGISTER UNEFFECTEDFigure 19. Master Reset Timing SequenceDATA (W0)XXXXX100WCLKFQUDREF CLKDAC STROBEINTERNAL CLOCKS DISABLEDFigure 20.Parallel-Load Power-Down Sequence/Internal OperationDATA (W0)XXXXX000WCLKFQUDREF CLKINTERNAL CLOCKS ENABLEDFigure 21.Parallel-Load Power-Up Sequence/Internal Operation–11–

(PARALLEL)DATA (W0)XXXXX011REQUIRED TO RESET CONTROL REGISTERSDATA (SERIAL)W32 = 0W33 = 0W34 = 0NOTE: AT LEAST FIRST 8 BITS OF 40-BIT SERIAL LOAD WORDARE REQUIRED TO SHIFT IN REQUIRED W32–W34 DATAWCLKFQUDENABLE SERIAL MODERESET CONTROL WORDSNOTE: FOR DEVICE START-UP IN SERIAL MODE, HARD-WIRE LEAD 2 AT “0”, LEAD 3 AT “1”, AND LEAD 4 AT “1”(SEE FIGURE 23).Figure 22.Serial-Load Enable Sequence2+V3AD9850BRSSUPPLY4Figure 23.Leads 2–4 Connection for Default Serial-Mode OperationDATA –W0W1W2W3W39FQUDWCLK 40 WCLK CYCLESFigure 24.Serial-Load Frequency/Phase Update SequenceTable IV.40-Bit Serial-Load Word Function AssignmentW0Freq-b0 (LSB)W14Freq-b14W28Freq-b28W1Freq-b1W15Freq-b15W29Freq-b29W2Freq-b2W16Freq-b16W30Freq-b30W3Freq-b3W17Freq-b17W31Freq-b31 (MSB)W4Freq-b4W18Freq-b18W32ControlW5Freq-b5W19Freq-b19W33ControlW6Freq-b6W20Freq-b20W34Power-DownW7Freq-b7W21Freq-b21W35Phase-b0 (LSB)W8Freq-b8W22Freq-b22W36Phase-b1W9Freq-b9W23Freq-b23W37Phase-b2W10Freq-b10W24Freq-b24W38Phase-b3W11Freq-b11W25Freq-b25W39Phase-b4 (MSB)W12Freq-b12W26Freq-b26W13Freq-b13W27Freq-b27–12–

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AD9850

DATA (7) –

W32=0W33=0W34=1W35=XW36=XW37=XW38=XW39=XFQUDWCLKFigure 25.Serial-Load Power-Down SequenceVCCVCCVCCVCCQOUT/QOUTBVINP/VINNDIGITALINIOUTIOUTBDAC Output Comparator Output Comparator Input Digital InputsFigure 26.AD9850 I/O Equivalent CircuitsPCB LAYOUT INFORMATIONEvaluation BoardsThe AD9850/CGPCB and AD9850/FSPCB evaluation boards(Figures 27–30) represent typical implementations of theAD9850 and exemplify the use of high frequency/high resolu-tion design and layout practices. The printed circuit board thatcontains the AD9850 should be a multilayer board that allowsdedicated power and ground planes. The power and groundplanes should be free of etched traces that cause discontinuitiesin the planes. It is recommended that the top layer of the multi-layer board also contain interspatial ground plane, which makesground available for surface-mount devices. If separate analogand digital system ground planes exist, they should be con-nected together at the AD9850 for optimum results.Avoid running digital lines under the device as these will couplenoise onto the die. The power supply lines to the AD9850should use as large a track as possible to provide a low-impedancepath and reduce the effects of glitches on the power supply line.Fast switching signals like clocks should be shielded withground to avoid radiating noise to other sections of the board.Avoid crossover of digital and analog signal paths. Traces onopposite sides of the board should run at right angles to eachother. This will reduce the effects of feedthrough through thecircuit board. Use microstrip techniques where possible.Good decoupling is also an important consideration. The analog(AVDD) and digital (DVDD) supplies to the AD9850 areindependent and separately pinned out to minimize couplingbetween analog and digital sections of the device. All analogand digital supplies should be decoupled to AGND and DGND,respectively, with high quality ceramic capacitors. To achievebest performance from the decoupling capacitors, they shouldbe placed as close as possible to the device, ideally right upagainst the device. In systems where a common supply is used todrive both the AVDD and DVDD supplies of the AD9850, it isrecommended that the system’s AVDD supply be used.Analog Devices, Inc., applications engineering support is avail-able to answer additional questions on grounding and PCBlayout. Call 1-800-ANALOGD.Two versions of evaluation boards are available for the AD9850,which facilitate the implementation of the device for bench-top analysis, and serve as a reference for PCB layout. TheAD9850/FSPCB is intended for applications where the devicewill primarily be used as frequency synthesizer. This versionfacilitates connection of the AD9850’s internal D/A converteroutput to a 50Ω spectrum analyzer input; the internal com-parator on the AD9850 DUT is not enabled (see Figure 28 forelectrical schematic of AD9850/FSPCB). The AD9850/CGPCBis intended for applications using the device in the clock genera-tor mode. It connects the AD9850’s DAC output to the internalcomparator input via a single-ended, 42 MHz low-pass, 5-pole Elliptical filter. This model facilitates the access of theAD9850’s comparator output for evaluation of the device as afrequency- and phase-agile clock source (see Figure 29 forelectrical schematic of AD9850/CGPCB).Both versions of the AD9850 evaluation boards are designed tointerface to the parallel printer port of a PC. The operatingsoftware runs under Microsoft® Windows and provides a user-friendly and intuitive format for controlling the functionalityand observing the performance of the device. The 3.5\" floppyprovided with the evaluation board contains an executable filethat loads and displays the AD9850 function-selection screen.The evaluation board may be operated with +3.3 V or +5 Vsupplies. The evaluation boards are configured at the factory foran external reference clock input; if the onboard crystal clocksource is used, remove R2.All trademarks are the property of their respective holders.REV. E

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AD9850

AD9850 Evaluation Board InstructionsRequired hardware/software:IBM compatible computer operating in a Windows environmentPrinter port, 3.5\" floppy drive and Centronics compatibleprinter cable.XTAL clock or signal generator—if using a signal generator, dcoffset the signal to one-half the supply voltage and apply atleast 3V p-p signal across the 50 Ω (R2) input resistor.Remove R2 for high Z clock input.AD9850 evaluation board software disk and AD9850/FSPCB orAD9850/CGPCB evaluation board.+5 V voltage supplySetup:Locate the “CLOCK” box and place the cursor in the frequencybox. Type in the clock frequency (in MHz) that you will beapplying to the AD9850. Click the LOAD button or press enteron the keyboard.Move the cursor to the OUTPUT FREQUENCY box and type inthe desired output frequency (in MHz). Click the “LOAD” buttonor press the enter key. The BUS MONITOR section of thecontrol panel will show the 32-bit word that was loaded into theAD9850. Upon completion of this step, the AD9850 outputshould be active and outputting your frequency information.Changing the output phase is accomplished by clicking on the“down arrow” in the OUTPUT PHASE DELAY box to makea selection and then clicking the LOAD button.Other operational modes (Frequency Sweeping, Sleep, SerialInput) are available to the user via keyboard/mouse control.The AD9850/FSPCB provides access into and out of the on-chipcomparator via test point pairs (each pair has an active input and aground connection). The two active inputs are labeled TP1 andTP2. The unmarked hole next to each labeled test point is aground connection. The two active outputs are labeled TP5 andTP6. Unmarked ground connections are adjacent to each of thesetest points.The AD9850/CGPCB provides BNC inputs and outputs associ-ated with the on-chip comparator and the onboard, 5th order,200 ohm input/output Z, elliptic 45 MHz low-pass filter. Jumper-ing (soldering a wire) E1 to E2, E3 to E4, and E5 to E6 connectsthe onboard filter and the midpoint switching voltage to thecomparator. Users may elect to insert their own filter and com-parator threshold voltage by removing the jumpers and insertinga filter between J7 and J6 and then providing a threshold voltageat E1.If you choose to use the XTAL socket to supply the clock to theAD9850, you must remove R2 (a 50 ohm chip resistor). Thecrystal oscillator must be either TTL or CMOS (preferably)compatible.Copy the contents of the AD9850 disk onto your hard drive(there are three files).Connect the printer cable from computer to the AD9850evaluation board.Apply power to AD9850 evaluation board. The AD9850 ispowered separately from the connector marked “DUT +V.”The AD9850 may be powered with 3.3V to +5 V.Connect external 50 ohm clock or remove R2 and apply a highZ input clock such as a crystal “can” oscillator.Locate the file called 9850REV2.EXE and execute that program.Monitor should display a “control panel” to allow operation ofthe AD9850 evaluation board.Operation:On the control panel, locate the box called “COMPUTER I/O.”Point to and click the selection marked LPT1 and then point tothe “TEST” box and click. A message will appear telling you ifyour choice of output ports is correct. Choose other ports asnecessary to achieve a correct setting. If you have trouble gettingyour computer to recognize any printer port, try the following:connect three 2K pull-up resistors from Pins 9, 8 and 7 of U3 to+5 V. This will assist “weak” printer port outputs in driving theheavy capacitance load of the printer cable. If troubles persist,try a different printer cable.Locate the “MASTER RESET” button with the mouse andclick it. This will reset the AD9850 to 0 Hz, 0 degrees phase.The output should be a dc voltage equal to the full-scale outputof the AD9850.–14–

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AD9850

C36CRPXJ1123456710111213141516PORT11718192021222324252627282930313233343536STROBEWWCLKCHECK+VC610␮F+5VC710␮FC20.1␮FC30.1␮FRRESETWWCLKFFQUDRRESET98765432FFQUDSTROBE10mARSETR13.9k⍀RRESET98765432U274HCT5748D7D6D5D4D3D2D1D118Q7Q6Q5Q4Q3Q2Q1Q11213141516171819D0D1D2D3D4D5D6D7J2+VH1#6D31D3D22D2D13D04D0D428D4D527D526D6H2#6H3#6H4#6BANANAJ3JACKSJ4+5VGNDMOUNTINGHOLESU1D1D6AD9850D725D7GND5DGND+V6DVDDWCLK7WCLKFQUD8FQUDCLKIN9CLKINGND10AGND+V11AVDD12RSET13QOUTDGND24GNDDVDD23+VRESET22RESETIOUT21IOUTB20AGND19GNDAVDD18DACBL17VINP16VINN15GNDGNDR61k⍀J5+VR71k⍀GNDTP1+VR525⍀R450⍀J6DAC OUTTO 50⍀CLKOETP514QOUTBCOMPARATORTP6OUTPUTSTP7U374HCT5748D7D6D5D4D3D2D1DCLK11STROBE8Q7Q6Q5Q4Q3Q2Q1QOE11213141516171819RESETWCLKFQUDCHECKTP8TP2COMPARATORTP3INPUTSTP4GNDGNDCLKINREMOVEWHENUSING Y1+5V14VCCR250⍀XTALOSCY1GND7OUT8+5VR102.2k⍀+5VRRESETR92.2k⍀R82.2k⍀R32.2k⍀+VC40.1␮FC50.1␮FFFQUDWWCLKSTROBEC80.1␮FC90.1␮FC100.1␮FFigure 27.AD9850/FSPCB Electrical SchematicCOMPONENT LISTIntegrated CircuitsU1U2, U3CapacitorsAD9850BRS (28-Lead SSOP)74HCT574 H-CMOS Octal Flip-Flop0.1 µF Ceramic Chip Capacitor10 µF Tantalum Chip Capacitor3.9 kΩ Resistor50 Ω Resistor2.2 kΩ Resistor25 Ω Resistor1 kΩ Resistor36-Pin D ConnectorBanana JackBNC ConnectorC2–C5, C8–C10C6, C7ResistorsR1R2, R4R3, R8, R9, R10R5R6, R7ConnectorsJ1J2, J3, J4J5, J6REV. E

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AD9850

a.AD9850/FSPCB Top Layerc.AD9850/FSPCB Power Planeb.AD9850/FSPCB Ground Planed.AD9850/FSPCB Bottom Layer Figure 28.AD9850/FSPCB Evaluation Board Layout–16–

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C36CRPXJ112RRESET34567101112131415FFQUD16P17O18RT19201212223242526272829303132WWCLK33CHECK343536STROBECOMPONENT LISTIntegrated CircuitsU1U2, U3CapacitorsC1C2–C5, C8–C10C6, C7C11C12C13C14C15REV. E

AD9850

J2+V74HCT574U2BANANAJ3H1H2H3H4JACKS+5V#6#6#6#69J4MOUNTING8D8Q12D0GNDHOLES200⍀ Z87D7Q13D1LOW PASS FILTER42MHz ELLIPTIC76D6Q14D2D31D3D428D4L1L261008CS1008CS5D5Q15D3D22D2D527D5680nH54D4Q16D4D13D143D3Q17AD9850U1D626D6E6E51910nH212C12D543D725D7J7BNC3.3pFC14D0D08.2pF2D2Q18D62GND5DGNDDGND24GND1D1Q19D7+V6DVDDDVDD23+VR4100k⍀R6200⍀C11CLKOE22pFC1333pFWCLK7WCLKRESET22RESET111FQUD8FQUDIOUT21R5100k⍀C1522pFSTROBECLKIN9CLKINIOUTB20GND10AGNDAGND19GNDR8R1100⍀+V11AVDD+V10mA3.9k⍀AVDD18R7RSET12RSETDACBL17J6200⍀13QOUTBNCVINP16J814QOUTBVINN15C1BNC470pFJ9E1E2E4E3J5+5VCLKINR9R10R11R374HCT574U32.2k⍀2.2k⍀2.2k⍀2.2k⍀REMOVER2WHEN50⍀RRESET98D8Q12RESETRRESETFFQUDWWCLKSTROBEUSING Y1WWCLK87D7Q13WCLK+5VFFQUD76D6Q14FQUD14RRESET655D5Q15CHECKXTALVCCOUT844D4Q16OSCY1GND33D3Q17722D2Q181D1Q19+V+5VCLKOE111+V+5VC2C3C5C8C9C10C6C70.1␮F0.1␮FC40.1␮F0.1␮F0.1␮F0.1␮F0.1␮FSTROBE10␮F10␮FFigure 29.AD9850/CGPCB Electrical SchematicResistorsAD9850BRS (28-Lead SSOP)R13.9 kΩ Resistor74HCT574 H-CMOS Octal Flip-FlopR250 Ω ResistorR3, R9, R10, R112.2 kΩ Resistor470 pF Ceramic Chip CapacitorR4, R5100 kΩ Resistor0.1 µF Ceramic Chip CapacitorR6, R7200 Ω Resistor10 µF Tantalum Chip CapacitorR8100 Ω Resistor22 pF Ceramic Chip CapacitorConnectors3.3 pF Ceramic Chip CapacitorJ2, J3, J4Banana Jack33 pF Ceramic Chip CapacitorJ5–J9BNC Connector8.2 pF Ceramic Chip Capacitor22 pF Ceramic Chip CapacitorInductorsL1910 nH Surface MountL2680 nH Surface Mount–17–

AD9850

a. AD9850/CGPCB Top Layerc. AD9850/CGPCB Power Planeb. AD9850/CGPCB Ground Planed. AD9850/CGPCB Bottom LayerFigure 30.AD9850/CGPCB Evaluation Board Layout–18–

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AD9850

OUTLINE DIMENSIONSDimensions shown in inches and (mm).28-Lead Shrink Small Outline Package(RS-28)REV. E

0.407 (10.34)0.397 (10.08)2815))))819432.67...55(7(( (1 2511103022.30...0001140.078 (1.98)PIN 10.07 (1.79)0.068 (1.73)0.066 (1.67)80.008 (0.203)0.02560.015 (0.38)00.002 (0.050)(0.65)0.009 (0.229)0.03 (0.762)BSC0.010 (0.25)SEATINGPLANE0.005 (0.127)0.022 (0.558)–19–

99/5–0–e5512CPRINTED IN U.S.A.