•Six Half-bridge Outputs Formed by Six High-side and Six Low-side Drivers
•Capable of Switching all Kinds of Loads (Such as DC Motors, Bulbs, Resistors, Capacitors and Inductors)
•RDSon Typically 1.0Ω at 25°C, Maximum 1.8Ω at 150°C•Up to 1A Output Current
•Very Low Quiescent Current IS < 20 µA in Standby Mode•Outputs Short-circuit Protected
•Overtemperature Prewarning and Protection•Undervoltage Protection
•Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature and Power Supply Fail•Serial Data Interface
•Operation Voltage up to 40V•Daisy Chaining Possible
•Serial Interface 5V Compatible, up to 2MHz Clock Frequency•
QFN24 Package
1.Description
The ATA6838 is a fully protected hex half-bridge driver designed in Smart Power SOItechnology, used to control up to 6 different loads by a microcontroller in automotiveand industrial applications.
Each of the six high-side and six low-side drivers is capable of driving currents up to1A. The drivers are internally connected to form 6 half-bridges and can be controlledseparately from a standard serial data interface. Therefore, all kinds of loads, such asbulbs, resistors, capacitors and inductors, can be combined. The IC especially sup-ports the application of H-bridges to drive DC motors.
Protection is guaranteed in terms of short-circuit conditions, overtemperature andundervoltage. Various diagnosis functions and a very low quiescent current in standbymode make a wide range of applications possible.
Automotive qualification referring to conducted interferences, EMC protection andESD protection gives added value and enhanced quality for the exacting requirementsof automotive applications.
Hex Half-bridge Driver with Serial Input ControlATA6838Preliminary 4954D–AUTO–10/08Figure 1-1.Block Diagram QFN24
SIS C TOLDH S 6L S 6H S 5L S 5H S 4L S 4HS3LS3HS2LS2HS1LS1SRR3, 4VSInput registerOuput registerPSFINHS C DH S 6L S 6H S 5L S 5H S 4L HS S43Serial interfaceChargepumpLS1TPDI19LS3HS2LS2HS1CLK18CS17INH12DO13ControllogicPower onreset24GNDFaultDetectFaultDetectFaultDetectFaultDetectFaultDetectFaultDetectFaultDetectFaultDetectFaultDetectFaultDetectFaultDetectFaultDetectUVprotection14VCC16GNDThermalprotection15GND711OUT18OUT25OUT32OUT423OUT520OUT6GND2
ATA6838[Preliminary]
4954D–AUTO–10/08
ATA6838[Preliminary]
2.Pin Configuration
Figure 2-1.
Pinning QFN 24, 5×5, 0.65mm pitch
NCOUT5OUT5 SENSEOUT6 SENSEOUT6DIOUT4 SENSEOUT4VSVSOUT3OUT3 SENSE1234562423222120191817161514137101112CLKCSGND SENSENCVCCDONote:
YWWDate code (Y = Year above 2000, WW = week number)ATAxyz Product nameZZZZZ Wafer lot numberALAssembly sub-lot number
Table 2-1.
Pin123456710111213141516
Pin Description QFN24
Symbol
Function
Half-bridge output 4; formed by internally connected power MOS high-side switch 4 and low-side switch 4
with internal reverse diodes; short circuit protection; overtemperature protection; diagnosis for short and open load
Power supply output stages HS4, HS5 and HS6Power supply output stages HS1, HS2 and HS3Output 3; see pin 1Internal bond to GNDOutput 2; see pin 1
OUT4 SENSEOnly for testability in final test
OUT4VSVSOUT3NCOUT2
OUT3 SENSEOnly for testability in final test
OUT2 SENSEOnly for testability in final testOUT1 SENSEOnly for testability in final test
OUT1INHDOVCCNC
Output 1; see pin 1
Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operation
Serial data output; 5V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first). Output will remain tri-stated unless device is selected by CS=low, therefore, several ICs can operate on one data output line onlyLogic supply voltage (5V)Internal bond to GND
GND SENSEGround; reference potential; internal connection to the lead frame; cooling tab
NCOUT2OUT2 SENSEOUT1 SENSEOUT1INH3
4954D–AUTO–10/08
Table 2-1.
Pin1718192021222324
Pin Description QFN24 (Continued)
SymbolCSCLKDIOUT6
Function
Chip select input; 5V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled
Serial clock input; 5V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (fmax = 2 MHz)
Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred firstOutput 6; see pin 1
OUT6 SENSEOnly for testability in final testOUT5 SENSEOnly for testability in final test
OUT5NC
Output 5; see pin 1Internal bond to GND
4
ATA6838[Preliminary]
4954D–AUTO–10/08
ATA6838[Preliminary]
3.Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronizedto CLK and is accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be trans-ferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CSis high, pin DO is in a tri-state condition. This output is enabled on the falling edge of CS. Outputdata will change their state with the rising edge of CLK and stay stable until the next rising edgeof CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1.
CSData Transfer Input Data Protocol
DISRR0LS11HS12LS23HS24LS35HS36LS47HS48LS59HS510LS611HS612OLD13SCT1415SICLKDOTPSLS1SHS1SLS2SHS2SLS3SHS3SLS4SHS4SLS5SHS5SLS6SHS6SCDINHPSFTable 3-1.
Bit01234567101112131415
Input Data Protocol
Input Register
SRRLS1HS1LS2HS2LS3HS3LS4HS4LS5HS5LS6HS6OLDSCTSI
Function
Status register reset (high = reset; the bits PSF, SCD and
overtemperature shutdown in the output data register are set to low)Controls output LS1 (high = switch output LS1 on)Controls output HS1 (high = switch output HS1 on)See LS1See HS1See LS1See HS1See LS1See HS1See LS1See HS1See LS1See HS1
Open load detection (low = on)
Programmable time delay for short circuit (shutdown delay high/low=12ms/1.5 ms)
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part is still powered)
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4954D–AUTO–10/08
Table 3-2.
Bit0
Output Data Protocol
Output (Status)
Register
TP
Function
Temperature prewarning: high = warning
(overtemperature shutdown see remark below)
Normal operation: high = output is on, low = output is offOpen-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched off)
Normal operation: high = output is on, low = output is offOpen-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is switched off)Description see LS1Description see HS1Description see LS1Description see HS1Description see LS1Description see HS1Description see LS1Description see HS1Description see LS1Description see HS1
Short circuit detected: set high, when at least one output is switched off by a short circuit condition
Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (pinINH). High = standby, low = normal operationPower supply fail: undervoltage at pin VS detected
1Status LS1
234567101112131415Note:
Status HS1Status LS2Status HS2Status LS3Status HS3Status LS4Status HS4Status LS5Status HS5Status LS6Status HS6SCDINHPSF
Bit 0 to 15 = high: overtemperature shutdown
Table 3-3.
Bit 15Bit 14(SI)(SCT)H
H
Status of the Input Register After Power on Reset
Bit 13
(OLD)H
Bit 12(HS6)L
Bit 11(LS6)L
Bit 10(HS5)L
Bit 9(LS5)L
Bit 8(HS4)L
Bit 7(LS4)L
Bit 6(HS3)L
Bit 5(LS3)L
Bit 4(HS2)L
Bit 3(LS2)L
Bit 2Bit 1(HS1)(LS1)L
L
Bit 0(SRR)L
6
ATA6838[Preliminary]
4954D–AUTO–10/08
ATA6838[Preliminary]
3.2
Power-supply Fail
In case of undervoltage at pin VS, an internal timer is started. When during a permanent under-voltage the delay time (tdUV) is reached, the power supply fail bit (PSF) in the output register isset and all outputs are disabled. When normal voltage is present again, the outputs are enabledimmediately. The PSF bit remains high until it is reset by the SRR bit in the input register.
3.3Open-load Detection
If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch anda pull-down current for each low-side switch is turned on (open-load detection current IHS1-6,ILS1-6). If VVS–VHS1-6 or VLS1-6 is lower than the open-load detection threshold (open-load condi-tion), the corresponding bit of the output in the output register is set to high. Switching on anoutput stage with OLD bit set to low disables the open load function for this output.
3.4Overtemperature Protection
If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperatureprewarning bit (TP) in the output register is set. When the temperature falls below the thermalprewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferringa complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO. After themicrocontroller has read this information, CS is set high and the data transfer is interrupted with-out affecting the state of the input and output registers.
If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs aredisabled and all bits in the output register are set high. The outputs can be enabled again whenthe temperature falls below the thermal shutdown threshold, Tj switch on, and when a high hasbeen written to the SRR bit in the input register. Thermal prewarning and shutdown thresholdhave hysteresis.
3.5Short-circuit Protection
The output currents are limited by a current regulator. Current limitation takes place when theovercurrent limitation and shutdown threshold (IHS1-6, ILS1-6) are reached. Simultaneously, aninternal timer is started. The shorted output is disabled when during a permanent short the delaytime (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-cir-cuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is setduring a short, the shorted output is disabled immediately and SCD bit is set. By writing a high tothe SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled.
3.6Inhibit
There are two ways to inhibit the ATA6838:•Set bit SI in the input register to 0•Switch pin INH to 0V
In both cases, all output stages are turned off but the serial interface stays active. The outputstages can be activated again by bit SI = 1 (when INH = VCC) or by pin INH switched back toVCC (when SI = 1).
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4954D–AUTO–10/08
4.Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.All values refer to GND pins.ParametersSupply voltage
Supply voltage t<0.5s; IS>–2ASupply voltage difference⏐VS_pin3–VS_pin4⏐ Logic supply voltageLogic input voltageLogic output voltageInput currentOutput currentOutput current
Junction temperature rangeStorage temperature range
Pin3, 43, 43, 41417 - 191312, 17 - 19
13
2, 5, 8, 11, 20, 23
SymbolVVSVVSΔVVSVVCCVDI, VCLK, VCS
VDO
IINH, IDI, ICLK, ICS
IDO
IOUT1 to IOUT6
TjTSTG
Value –0.3 to +40
–1150 –0.3 to +7 –0.3 to VVCC +0.3 –0.3 to VVCC +0.3 –10 to +10 –10 to +10Internally limited, see“Output Specification” in Section 7. on page 9
–40 to +150 –55 to +150
°C°CUnitVVmVVVVmAmA
5.Thermal Resistance
Table 5-1.
ParameterJunction pinJunction ambient
QFN24: Depends on the PCB-board
Test Conditions
Pin16
SymbolRthJPRthJA
Min.
Typ.
Max.< 535
UnitK/WK/W
6.Operating Range
ParameterSupply voltageLogic supply voltageLogic input voltageSerial interface clock frequency
Junction temperature range
Test Conditions
Pin3, 41412, 17 - 19
SymbolVVSVVCCVINH, VDI, VCLK,
VCS
fCLKTj
–40Min.VUV(1)4.75 –0.3
Typ.
Max.405.25VVCC2+150
UnitVVVMHz°C
8
ATA6838[Preliminary]
4954D–AUTO–10/08
ATA6838[Preliminary]
7.Electrical Characteristics
7.5V < VS < 40V; 4.75 < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.No.1
Parameters
Current ConsumptionTotal quiescent current (VS and all outputs to VS)
VS = 33VVCC = 0V or
VCC = 5V, bit SI = low orVCC = 5V, pin INH = lowOutput pins to VS and GND
4.75V < VVCC < 5.25V, INH or bit SI = low VVS < 28V normal operation, all output stages off
VVS < 28V normal
operation, all output low stages on, no loadVVS < 28V normal operation, all output high stages on, no load4.75 < VVCC < 5.25V, normal operationTest Conditions
Pin
SymbolMin.Typ.Max.UnitType*
1.13, 4
IVS
2µAA
1.21.3
Quiescent current (VCC)Supply current (VS)
143, 4
IVCCIVS
0.8
201.2
µAmA
AA
1.4Supply current (VS)3, 4
IVS
10mAA
1.51.622.133.13.23.33.43.544.14.24.34.44.54.6
Supply current (VS)Supply current (VCC)
3, 414
IVSIVCC
16150
mA µA
AA
Internal Oscillator FrequencyFrequency (time base for delay timers)
Undervoltage Detection, Power-on ResetPower-on reset thresholdPower-on reset delay time
Undervoltage detection threshold
Undervoltage detection hysteresis
Undervoltage detection delay
Thermal Prewarning and ShutdownThermal prewarningThermal prewarningThermal prewarning hysteresisThermal shutdownThermal shutdownThermal shutdown hysteresis
TjPWsetTjPWresetTjPWTj switch offTj switch onTj switch off
150135120105
1451301517516015
200185170155
°C°CK°C°CK
BBBBBB
After switching on VVCC
1414
VVCCtdPorVUVΔVUVtdUV
72.3305.5
0.4
21
2.795
3.0 V1607.0
µsVVms
AAAAA
fOSC
19
45
kHz
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameterNotes:
1.Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
9
4954D–AUTO–10/08
7.Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75 < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.No.4.7
ParametersRatio thermal shutdown/thermal prewarningRatio thermal shutdown/thermal prewarning
Output Specification (LS1-LS6, HS1-HS6) 7.5V < VVS < 40VOn resistance
IOut = 600 mA
2, 5, 8, 11, 20, 232, 5, 8, 11, 20, 232, 5, 8, 11, 20, 232, 5, 8, 11, 20, 232, 5, 8, 11, 20, 232, 5, 8, 11, 20, 232, 5, 8, 11, 20, 232, 5, 8, 11, 20, 232, 5, 8, 11, 20, 23
RDS OnL
1.8
Ω
A
Test Conditions
Pin
SymbolTj switch off/
TjPW set
Min.1.05
Typ.1.2
Max.UnitType*B
4.855.1
Tj switch on/ TjPW reset
1.051.2A
5.2On resistance
IOut = –600 mARDS OnH
1.8ΩA
5.3
High-side output leakage
VOut1-6 = 0V
current (total quiescent
all output stages off
current see 1.1)
Low-side output leakage
VOut1-6 = VS
current (total quiescent
all output stages off
current see 1.1)Inductive shutdown energy
Overcurrent limitation
VVS = 13V
and shutdown threshold
Overcurrent limitation
VVS = 13V
and shutdown threshold
Overcurrent limitation
20V < VVS < 40V
and shutdown threshold
Overcurrent limitation
20V < VVS < 40V
and shutdown thresholdOvercurrent shutdown delay time
Overcurrent shutdown delay time
High-side open load detection currentLow-side open load detection current
Input register bit 14 (SCT) = lowInput register
bit 14 (SCT) =HighInput register bit 13 (OLD) = low, output offInput register bit 13 (OLD) = low, output off
IOut1-6
–15 µAA
5.4
IOut1-6
120 µAA
5.5
Woutx
15mJD
5.6
ILS1-6
1.01.31.7AA
5.7
IHS1-6
–1.7 –1.3–1.0AA
5.8
ILS1-6
1.01.32.0AC
5.95.105.115.12
IHS1-6tdSdtdSd
–2.00.97 –1.5
–1.31.512
–1.02.117 –0.4
AmsmsmA
CAAA
2, 5, 8, 11, 20, 232, 5, 8, 11, 20, 23
IOut1-3H
5.13
IOut1-3L
0.41.5mAA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameterNotes:
1.Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
10
ATA6838[Preliminary]
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ATA6838[Preliminary]
7.Electrical Characteristics (Continued)
7.5V < VS < 40V; 4.75 < VCC < 5.25V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins.No.5.14
ParametersOpen load detection current ratioHigh-side open load detection voltageLow-side open load detection voltage
Input register bit 13 (OLD) = low, output offInput register bit 13 (OLD) = low, output offTest Conditions
Pin
SymbolIOLoutLX/IOLoutHXVOut1-6H
Min.1.05
Typ.1.2
Max.2
UnitType*
2, 5, 8, 11, 20, 232, 5, 8, 11, 20, 232, 5, 8, 11, 20, 23
5.150.6
2.5V
A
5.165.175.185.195.205.2166.16.26.36.477.17.27.37.47.588.18.28.3
VOut1-6Ltdontdontdofftdofftdon – tdoff
0.62202020
V µs µs µs
AAAAAA
High-side output switch VVS = 13V
RLoad=30Ωon delay(1)
Low-side output switch
on delay(1)
VVS = 13VRLoad=30Ω
High-side output switch VVS =13V off delay(1)RLoad = 30ΩLow-side output switch off delay(1)
VVS =13VRLoad = 30Ω
3µs
1
µs
Dead time between
V=13V
corresponding high- and VS
RLoad = 30Ω
low-side switches Inhibit Input
Input voltage low-level threshold
Input voltage high-level threshold
Hysteresis of input voltage
Pull-down currentInput voltage low-level threshold
Input voltage high-level threshold
Hysteresis of input voltage
Pull-down current pin DI,
VDI, VCLK = VVCC
CLK
Pull-up current pinCS
VCS= 0V
Serial Interface: Logic Output DOOutput voltage low level IOL = 3 mA Output voltage high level IOL = –1 mA Leakage current(tri-state)
VCS = VVCC,
0V < VDO < VVCC VINH = VVCC
Serial Interface: Logic Inputs DI, CLK, CS
VILVIHΔVIIPDVILVIHΔVIIPDSIIPUSIVDOLVDOHIDO
0.3 ×VVCC
0.7 ×VVCC
100100.3 ×VVCC
0.7 ×VVCC
502 –50
50050 –20.5
VVCC – 0.7V –10
+1070080
VVmV µA
AAAA
VVmVµA µAVV µA
AAAAAAAA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameterNotes:
1.Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of
final level. Device not in standby for t > 1 ms.
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4954D–AUTO–10/08
8.Serial Interface: Timing
Parameters
DO enable after CS falling edgeDO disable after CS rising edgeDO fall timeDO rise timeDO valid timeCS setup timeCS setup timeCS high timeCS high timeCLK high timeCLK low timeCLK period timeCLK setup timeCLK setup timeDI setup timeDI hold time
Input register bit14 (SCT) = high
Input register bit14 (SCT) = low
Test ConditionsCDO = 100 pFCDO = 100 pFCDO = 100 pFCDO = 100 pFCDO = 100 pF
Pin13131313131717171718181818181919
Timing Chart No.Symbol
12--104956-731112
tENDOtDISDOtDOftDOrtDOValtCSSethltCSSetlhtCShtCShtCLKhtCLKltCLKptCLKSethltCLKSetlhtDIsettDIHold
225225172.12252255002252254040
Min.Typ.Max.Unit
200200100100200
nsnsnsnsnsnsnsmsmsnsnsnsnsnsnsns
12
ATA6838[Preliminary]
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ATA6838[Preliminary]
Figure 8-1.
Serial Interface Timing Diagram with Chart Numbers
12CSDO9CS47CLK5368DI11CLK1012DOInputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.2 × VCCOutput DO: High level = 0.8 × VCC, low level = 0.2 × VCC4954D–AUTO–10/08
13
9.Noise and Surge Immunity
Parameters
Conducted interferencesInterference suppressionESD (Human Body Model)CDM (Charge Device Model)MM (Machine Model)Note:
1.Test pulse 5: Vvbmax = 40V
Test ConditionsISO 7637-1VDE 0879 Part 2ESD S 5.1ESD STM5.3ESD STM5.2
ValueLevel 4(1)Level 54 kV500V200V
10.Application Circuit
Figure 10-1.Application Circuit
VSBYT41DVSInput registerOuput registerPSFINHS C DH S 6L S 6H S 5L S 5H S 4L HS S43Serial interface+VCCU5021M EnableWatchdogTriggerResetSIS C TOLDH S 6L S 6H S 5L S 5H S 4L S 4HS3LS3HS2LS2HS1LS1SRRVbatt 24VChargepumpLS1TPGNDDILS3HS2LS2HS1GNDGNDCLKMicrocontrollerGNDCSFaultDetectFaultDetectFaultDetectFaultDetectFaultDetectFaultDetectUVprotectionVCCPower onresetVCCINHControllogicDO+VCC 5VGNDVCCFaultDetectFaultDetectFaultDetectFaultDetectFaultDetectFaultDetectGNDThermalprotectionGNDGNDOUT1OUT2OUT3OUT4OUT5OUT6MMMMM14
ATA6838[Preliminary]
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ATA6838[Preliminary]
10.1
Application Notes
•Connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins.
•Recommended value for capacitors at VS:
Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and
reverse-conducting current IHSX (see Section 4. “Absolute Maximum Ratings” on page 8).•Recommended value for capacitors at VCC:
Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF.
•To reduce thermal resistance, place cooling areas on the PCB as close as possible to GND pins and to the die paddle in QFN24.
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4954D–AUTO–10/08
11.Ordering Information
Extended Type NumberATA6838-PXQW
PackageQFN24
Remarks
Taped and reeled, Pb-free
12.Package Information
Package: QFN 24 - 5 x 5 Exposed pad 3.6 x 3.6(acc. JEDEC OUTLINE No. MO-220)Dimensions in mmNot indicated tolerances ±0.050.9±0.10.05-0.052410.41819+053.6241technical drawingsaccording to DINspecifications60.31312760.65 nom.Drawing-No.: 6.543-5122.01-4Issue: 1; 15.11.053.2516
ATA6838[Preliminary]
4954D–AUTO–10/08
ATA6838[Preliminary]
13.Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document.Revision No.
History
• Features on page 1 changed
• Table 2-1 “Pin Description QFN242” on pages 3 to 4 changed• Section 4 “Abs.Max.Ratings” on page 8 changed• Section 5 “Thermal Resistance” on page 8 changed• Section 6 “Operating Range” on page 8 changed
• Section 7 “Electrical Characteristics” numbers 1.1, 1.2, 1.6, 4.1 to 4.7, 5.3, 5.4 and 5.6 to 5.9 on pages 9 to 10 changed
• Section 8 “Serial Interface: Timing” on page 12 changed• Section 9 “Noise and Surge Immunity” on page 14 changed• Section 11 “Ordering Information” on page 16 changed
• Section 7 “Electrical Characteristics” numbers 5.15 and 5.16 on page 10 changed
• Section 9 “Noise and Surge Immunity” on page 14 changed
• Put datasheet in a new template
• Section 7 “Electrical Characteristics” numbers 1.5, 3.1, 5.15 and 8.2 on pages 9 to 11 changed
4954D-AUTO-10/08
4954C-AUTO-09/07
4954B-AUTO-07/07
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4954D–AUTO–10/08
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4954D–AUTO–10/08
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