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专利名称：Multi-processor system
发明人：Takeshi Shimada,Tatsuru Nakagaki,Akihiro
Kobayashi
申请号：US11285184申请日：20051123公开号：US07320056B2公开日：20080115
专利附图：
摘要：Data transmission for writing data into a shared memory is performed by a high-speed dedicated line provided between each processor and the shared memory. When aprocessor performs writing to a shared memory space, the processor notifies an update
notification bus corresponding to the conventional global bus, to which address theupdate is to be performed. The other processors which have detected this notificationinhibit access to that address and wait for the write data to be sent to the address via thededicated line. When the data has arrived, the data is written into the correspondingaddress. Here, the data is also written into the corresponding address, therebymaintaining the cache coherency. Moreover, when transmitting a write address, it isnecessary to acquire the bus use right while data transmission is performed by using thededicated line, which significantly reduces the time required for acquiring the bus useright.
申请人：Takeshi Shimada,Tatsuru Nakagaki,Akihiro Kobayashi
地址：Kawasaki JP,Kawasaki JP,Kawasaki JP
国籍：JP,JP,JP
代理机构：Staas & Halsey LLP
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