计数器

一、一般计数器

 ENTITY wz6 is PORT(clk: IN Std_Logic;

 q: OUT Std_Logic_vector(3 downto 0));  END wz6;

 ARCHITECTURE a OFwz6 IS

 signal q1:std_logic_vector(3 downto 0);  BEGIN  process(clk)  begin

 if clk'event and clk ='1' then  q1<=q1+1;  end if;  q<=q1;

 end process;  end a;

二、带进位输出——分频——数控分频 （1）带进位输出——分频

ENTITY fenpin IS

PORT( CLK:IN STD_LOGIC; Q: out STD_LOGIC_VECTOR(3 DOWNTO 0); CO:OUT STD_LOGIC); END fenpin;

ARCHITECTURE fen OF fenpin IS

SIGNAL Q1: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

PROCESS(CLK) BEGIN

IF CLK'EVENT AND CLK='1' THEN if q1=\"1111\"

then q1<=\"0000\";co<='1'; else q1<=q1+1;co<='0'; END IF; end if;

END PROCESS; q<=q1; END

fen;

（2）数控分频——乐曲演奏

①思路一：0——D(归零法且：设为信号则相当于用LD清零，即最后状态能留住)

RD清零，即最后状态不能留住）

以上还要根据具体的语句

例1： library ieee;

use ieee.std_logic_11.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity skfp1 is

port(clk:in std_logic;

d:in std_logic_vector(7 downto 0); fout:out std_logic); end skfp1;

architecture a of skfp1 is

signal q: std_logic_vector(7 downto 0);

begin

process(clk)

begin

if clk' event and clk='1' then q<=q+1; end if;

if q=d then q<=\"00000000\" ;fout<='1'; else fout<='0'; end if;

end process; end a;

仿真成功

而稍加改动，则

例2

library ieee;

use ieee.std_logic_11.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity skfp1 is

port(clk:in std_logic;

d:in std_logic_vector(7 downto 0); fout:out std_logic); end skfp1;

architecture a of skfp1 is

signal q: std_logic_vector(7 downto 0);

begin

process(clk)

begin

if clk' event and clk='1' then q<=q+1;

if q=d then q<=”00000000” ;fout<=‘1’； else fout<=’0’; end if; end if; end process; end a;

问题：输入07，频率反而比33分得的频率低。但如果不是数控分频，单是任意固定模数的计数器，则没有问题 若红笔改为下面，则成功 IF Q<=D THEN

IF CLK'EVENT AND CLK='1' THEN Q<=Q+1;CO<='0'; END IF;

ELSe Q<=\"00000000\" ;CO<='1'; end if;

END PROCESS;

②思路2：D——计数器满（预置补数法） library ieee;

use ieee.std_logic_11.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity skfp is

port(clk:in std_logic;

d:in std_logic_vector(7 downto 0); fout:out std_logic); end skfp;

architecture a of skfp is

signal q: std_logic_vector(7 downto 0);

begin

process(clk)

begin

if clk' event and clk='1' then if q = \"11111111\" then q <= d; fout<='1'; else

q<=q+1; fout<='0'; end if; end if;

end process; end a;

注：仿真时，仿真时间要设的长一些，2微秒不行，10微秒可以，输入数据要设为二进制，十六进制不行（CYCLON系列），而7128系列可以设为十六进制。以上仿真图，输入数据持续时间还应再长一些。

三、带使能端、进位输出端

ENTITY fenpin1 IS

PORT( CLK,en:IN STD_LOGIC; Q: out STD_LOGIC_VECTOR(3 DOWNTO 0); CO:OUT STD_LOGIC); END fenpin1;

ARCHITECTURE fen OF fenpin1 IS

SIGNAL Q1: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

PROCESS(CLK)

BEGIN

if en='1' then

IF CLK'EVENT AND CLK='1' THEN if q1=\"1111\"

then q1<=\"0000\";co<='1'; else q1<=q1+1;co<='0'; END IF; end if; end if;

END PROCESS; q<=q1; END fen;

四、十进制计数器（加法式、减法式）

1、模47加法式（任意模数）Cyclon仿真成功 LIBRARY IEEE;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_11.ALL; ENTITY JS47 IS

PORT(CLK:IN STD_LOGIC;

QH,QL: BUFFER STD_LOGIC_VECTOR( 3downto 0)); END JS47;

ARCHITECTURE A OF JS47 IS BEGIN

PROCESS(CLK) BEGIN

IF CLK' EVENT AND CLK='1' THEN IF QL=\"1001\" THEN

QL<=\"0000\";QH<=QH+1;

ELSIF QH=\"0100\" AND QL=\"0110\" THEN QH<=\"0000\";QL<=\"0000\"; ELSE QL<=QL+1; END IF; END IF;

END PROCESS; END A;

2、模23减法式可显示 library ieee;

use ieee.std_logic_11.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity js23_1 is

port(clk : in std_logic;

seg1: out std_logic_vector(6 downto 0); seg2: out std_logic_vector(6 downto 0); co: out std_logic ); end js23_1;

architecture a of js23_1 is

signal q1: std_logic_vector(4 downto 0); signal rst : std_logic;

signal BCD : std_logic_vector(7 downto 0); begin

process(clk) begin

if rst='1' then q1<=\"10110\"; elsif clk'event and clk='1' then q1<=q1-1; end if;

end process;

rst<='1' when q1=\"00000\" else '0';

co<=rst;

BCD<=\"00000000\" WHEN q1=\"00000000\" else \"00000001\" WHEN q1=\"00000001\" else

\"00000010\" WHEN q1=\"00000010\" else \"00000011\" WHEN q1=\"00000011\" else \"00000100\" WHEN q1=\"00000100\" else \"00000101\" WHEN q1=\"00000101\" else \"00000110\" WHEN q1=\"00000110\" else \"00000111\" WHEN q1=\"00000111\" else \"00001000\" WHEN q1=\"00001000\" else \"00001001\" WHEN q1=\"00001001\" else \"00010000\" WHEN q1=\"00001010\" else \"00010001\" WHEN q1=\"00001011\" else \"00010010\" WHEN q1=\"00001100\" else \"00010011\" WHEN q1=\"00001101\" else \"00010100\" WHEN q1=\"00001110\" else \"00010101\" WHEN q1=\"00001111\" else \"00010110\" WHEN q1=\"00010000\" else \"00010111\" WHEN q1=\"00010001\" else \"00011000\" WHEN q1=\"00010010\" else \"00011001\" WHEN q1=\"00010011\" else \"00100000\" WHEN q1=\"00010100\" else \"00100001\" WHEN q1=\"00010101\" else \"00100010\" WHEN q1=\"00010110\" else \"00000000\";

seg1<=\"0111111\" when BCD(3 downto 0)=\"0000\" else \"0000110\" when BCD(3 downto 0)=\"0001\" else \"1011011\" when BCD(3 downto 0)=\"0010\" else \"1001111\" when BCD(3 downto 0)=\"0011\" else \"1100110\" when BCD(3 downto 0)=\"0100\" else \"1101101\" when BCD(3 downto 0)=\"0101\" else \"1111101\" when BCD(3 downto 0)=\"0110\" else \"0000111\" when BCD(3 downto 0)=\"0111\" else \"0000111\" when BCD(3 downto 0)=\"0111\" else \"0000111\" when BCD(3 downto 0)=\"0111\" else \"1111111\" when BCD(3 downto 0)=\"1000\" else \"1101111\" when BCD(3 downto 0)=\"1001\" else \"0000000\";

seg2<=\"0111111\" when BCD(7 downto 4)=\"0000\" else \"0000110\" when BCD(7 downto 4)=\"0001\" else \"1011011\" when BCD(7 downto 4)=\"0010\" else \"1001111\" when BCD(7 downto 4)=\"0011\" else \"1100110\" when BCD(7 downto 4)=\"0100\" else \"1101101\" when BCD(7 downto 4)=\"0101\" else \"1111101\" when BCD(7 downto 4)=\"0110\" else \"0000111\" when BCD(7 downto 4)=\"0111\" else \"0000111\" when BCD(7 downto 4)=\"0111\" else

\"0000111\" when BCD(7 downto 4)=\"0111\" else \"1111111\" when BCD(7 downto 4)=\"1000\" else \"1101111\" when BCD(7 downto 4)=\"1001\" else \"0000000\"; end a;

3、模23（31减至8）计数器——倒计时 library ieee;

use ieee.std_logic_11.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity jishu is

port(clk:in std_logic;

q:out std_logic_vector(4 downto 0)); end jishu;

architecture ss of jishu is

signal oo: std_logic_vector(4 downto 0); begin

process(clk,oo) begin

if oo>=\"01001\" then

if clk'event and clk='1' then oo<=oo-1; end if;

else oo<=\"11111\"; end if; q<=oo;

end process; end ss;

五、占空比均匀、占空比可调计数器

（1）占空比均匀 ENTITY fenfen IS

PORT( CLK:IN STD_LOGIC; Q: out STD_LOGIC_VECTOR(3 DOWNTO 0); CO:OUT STD_LOGIC); END fenfen;

ARCHITECTURE fen OF fenfen IS

SIGNAL Q1: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

PROCESS(CLK) BEGIN

IF CLK'EVENT AND CLK='1' THEN

if q1=\"1111\" then q1<=\"0000\"; else q1<=q1+1; END IF; end if;

END PROCESS;

PROCESS(Q1) BEGIN

IF Q1<=\"0111\" THEN CO<='0'; ELSE CO<='1'; END IF;

END PROCESS; q<=q1; END fen;

（2）占空比可调 LIBRARY IEEE;

USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_11.ALL; ENTITY PL_ASK1 IS

PORT(CLK,START:IN STD_LOGIC; F:OUT STD_LOGIC); END PL_ASK1;

ARCHITECTURE A OF PL_ASK1 IS SIGNAL Q: INTEGER RANGE 0 TO 15;

BEGIN

PROCESS(CLK) BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF START='0' THEN Q<=0; F<='0';--------若不加F<='0'，则当START='0'时，F赶到什么值就

是什么

ELSIF Q<=2 THEN F<='1';Q<=Q+1; ------ 改变“Q≤”后的值，可改变占空比； ELSIF Q=15 THEN F<='0';Q<=0; -------改变Q后的值，可改变分频比 ELSE F<='0';Q<=Q+1; END IF; END IF;

END PROCESS;

END A;

六、变模计数器——交通灯控制系统

（1）模9减、模3减、模7减依次循环进行，更接近交通灯：先红灯，再黄灯、再绿灯，再红、黄、绿。。。东西与南北各一套变模计数器。问题：每次计数初始时多一个1111的状态，是时序问题 library ieee;

use ieee.std_logic_11.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity bianmo2 is

port(clk,reset:in std_logic;

q: out std_logic_vector(3 downto 0)); end bianmo2;

architecture behave of bianmo2 is type states is(st0,st1,st2,st3,st4,st5); signal s:states;

signal q1:std_logic_vector(3 downto 0); begin

process(clk,reset) begin

if reset ='1' then s<=st0;

elsif clk'event and clk ='1' then case s is

when st0=> q1<=\"1001\";s<=st1;

when st1=>q1<=q1-1;if q1=\"0000\" then s<=st2;else s<=st1;end if;

when st2=>q1<=\"0011\";s<=st3;

when st3=>q1<=q1-1;if q1=\"0000\" then s<=st4;else s<=st3;end if; when st4=>q1<=\"0111\";s<=st5;

when st5=>q1<=q1-1;if q1=\"0000\" then s<=st0;else s<=st5;end if; end case; end if;

end process; q<=q1; end behave;

注：此状态机主控进程若为2个，则计数混乱，不受脉冲控制，因2进程的状态机的CASE语句因无CLK控制，所以此进程的计数为没有章法的

（2）

问题：仿真时首次a=“00”时，状态不准，其余全部正确。

Library IEEE;

USE IEEE.std_logic_11.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all; -----

Entity jsq Is

PORT( a: buffer std_logic_vector(1 DOWNTO 0); cp:in std_logic; co:buffer std_logic; QL,QH:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); End jsq; -------

Architecture behavior of jsq IS ---signal n : std_logic; BEGIN PROCESS(CP) begin ---n<=a; ---------------

IF(CP'EVENT AND CP='1') THEN IF a=\"00\" then

IF (QH=2 and QL=2) THEN QH<=\"0000\";QL<=\"0000\";co<='1'; elsif (QL=9) THEN QL<=\"0000\";QH<=QH+1;co<='0'; else QL<=QL+1;co<='0'; end if;

------------------------------------------------------------------------ elsif a=\"01\" then if (QH=1 and QL=2) THEN QH<=\"0000\";QL<=\"0000\";co<='1'; elsif (QL=9) THEN QL<=\"0000\";QH<=QH+1;co<='0'; else QL<=QL+1;co<='0'; end if;

------------------------------------------------------------------------- elsif a=\"10\" then

if (QH=3 and QL=2) THEN QH<=\"0000\";QL<=\"0000\";co<='1'; elsif (QL=9) THEN QL<=\"0000\";QH<=QH+1;co<='0'; else QL<=QL+1;co<='0'; end if;

------------------------------------------------------------------------- elsif a=\"11\" then

if (QH=4 and QL=2) THEN QH<=\"0000\";QL<=\"0000\";co<='1'; elsif (QL=9) THEN QL<=\"0000\";QH<=QH+1;co<='0'; else QL<=QL+1;co<='0'; end if;

-------------------------------------------------------------------------------

end if; end if;

END PROCESS; --------------------- PROCESS begin

wait until QH<=\"0000\" and QL<=\"0000\";a<=a+1; -- 红笔语句改成co'EVENT AND co='1' 则没有任何问题 END PROCESS; ------------------ END behavior;