元器件交易网www.cecb2b.com CD54AC112, CD74AC112DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESETSCHS325 – JANUARY 2003DAC Types Feature 1.5-V to 5.5-V OperationDDDDDand Balanced Noise Immunity at 30% of theSupply VoltageSpeed of Bipolar F, AS, and S, WithSignificantly Reduced Power ConsumptionBalanced Propagation Delays±24-mA Output Drive Current– Fanout to 15 F DevicesSCR-Latchup-Resistant CMOS Process andCircuit DesignExceeds 2-kV ESD Protection PerMIL-STD-883, Method 3015CD54AC112...FPACKAGECD74AC112...E OR M PACKAGE(TOP VIEW)1CLK1K1J1PRE1Q1Q2QGND12345678161514131211109VCC1CLR2CLR2CLK2K2J2PRE2Qdescription/ordering informationThe ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PREand CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred tothe outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level andis not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputsmay be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggleflip-flops by tying J and K high.ORDERING INFORMATIONTAPDIP – E–5555°C to 125Cto125°CSOICMSOIC – MCDIP – FPACKAGE†TubeTubeTape and reelTubeORDERABLEPART NUMBERCD74AC112ECD74AC112MCD74AC112M96CD54AC112F3ATOP-SIDEMARKINGCD74AC112EAC112MCD54AC112F3A†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelinesare available at www.ti.com/sc/package.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.Copyright 2003, Texas Instruments IncorporatedOn products compliant to MIL-PRF-38535, all parameters are testedunless otherwise noted. On all other products, productionprocessing does not necessarily include testing of all parameters.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•1元器件交易网www.cecb2b.comSCHS325 – JANUARY 2003CD54AC112, CD74AC112DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESETFUNCTION TABLE(each flip-flop)INPUTSPRELHLHHHHHCLRHLLHHHHHCLKXXX↓↓↓↓HJXXXLHLHXKXXXLLHHXOUTPUTSQHLH†Q0HLToggleQ0Q0QLHH†Q0LH †Output states are unpredictable if PRE and CLR go highsimultaneously after both being low at the same time.logic diagram (positive logic)QPREKCLKQCLRJabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 VInput clamp current, IIK (VI < 0 V or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mAOutput clamp current, IOK (VO < 0 V or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAContinuous output current, IO (VO > 0 V or VO < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mAContinuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mAPackage thermal impedance, θJA (see Note 2):E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/WM package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/WStorage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES:1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.2.The package thermal impedance is calculated in accordance with JESD 51-7.2POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com CD54AC112, CD74AC112DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESETSCHS325 – JANUARY 2003recommended operating conditions (see Note 3)TA = 25°CMINVCCVIHSupply voltageHigh-level input voltageVCC = 1.5 VVCC = 3 VVCC = 5.5 VVCC = 1.5 VVILVIVOIOHIOL∆t/∆vLow-level input voltageInput voltageOutput voltageHigh-level output currentLow-level output currentInputtransitionriseorfallrateInput transition rise or fall rateVCC = 4.5 V to 5.5 VVCC = 4.5 V to 5.5 VVCC = 1.5 V to 3 VVCC = 3.6 V to 5.5 VVCC = 3 VVCC = 5.5 V001.51.22.13.850.30.91.65VCCVCC–2424502000MAX5.5–55°C to125°CMIN1.51.22.13.850.30.91.65VCCVCC–2424502000MAX5.5–40°C to85°CMIN1.51.22.13.850.30.91.65VCCVCC–24245020VVmAmAns/VVVMAX5.5VUNITNOTE 3:All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.electrical characteristics over recommended operating free-air temperature range (unlessotherwise noted)PARAMETERTEST CONDITIONSVCC1.5 VIOH = –50 µAVOHVI = VIH or VILIOH = –4 mAIOH = –24 mAIOH = –50 mA†IOH = –75 mA†IOL = 50 µAVOLVI = VIH or VILIOL = 12 mAIOL = 24 mAIOL = 50 mA†IOL = 75 mA†IIICCCiVI = VCC or GNDVI = VCC or GND,IO = 03 V4.5 V3 V4.5 V5.5 V5.5 V1.5 V3 V4.5 V3 V4.5 V5.5 V5.5 V5.5 V5.5 V±0.1410±180100.10.10.10.360.360.10.10.10.50.51.651.65±14010µAµApFTA = 25°CMIN1.42.94.42.583.94MAX–55°C to125°CMIN1.42.94.42.43.73.853.850.10.10.10.440.44VMAX–40°C to85°CMIN1.42.94.42.483.8VMAXUNIT†Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimizepower dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.POST OFFICE BOX 655303 DALLAS, TEXAS 75265•3元器件交易网www.cecb2b.comSCHS325 – JANUARY 2003CD54AC112, CD74AC112DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESET timing requirements over recommended operating free-air temperature range, VCC = 1.5 V (unlessotherwise noted)–55°C to125°CMINfclocktwtsuthtrecClock frequencyPulsedurationPulse durationSetup time, before CLK↓Hold time, after CLK↓Recovery time, before CLK↓CLK high or lowCLR or PRE lowJ or KJ or KCLR↑or PRE↑635650031MAX8554944027–40°C to85°CMINMAX9MHznsnsnsnsUNITtiming requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V(unless otherwise noted)–55°C to125°CMINfclocktwtsuthtrecClock frequencyPulsedurationPulse durationSetup time, before CLK↓Hold time, after CLK↓Recovery time, before CLK↓CLK high or lowCLR or PRE lowJ or KJ or KCLR↑or PRE↑76.35.603.5MAX7165.54.903..1–40°C to85°CMINMAX81MHznsnsnsnsUNITtiming requirements over recommended operating free-air temperature0 range, VCC = 5 V ± 0.5 V(unless otherwise noted)–55°C to125°CMINfclocktwtsuthtrecClock frequencyPulsedurationPulse durationSetup time, before CLK↓Hold time, after CLK↓Recovery time, before CLK↓CLK high or lowCLR or PRE lowJ or KJ or KCLR↑or PRE↑54.5402.5MAX1004.43.93.502.2–40°C to85°CMINMAX114MHznsnsnsnsUNIT4POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com CD54AC112, CD74AC112DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESETSCHS325 – JANUARY 2003switching characteristics over recommended operating free-air temperature range, VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)PARAMETERfmaxtPLHtPHLCLKCLR or PRECLKCLR or PREQQQ or QQorQQ or QFROM(INPUT)TO(OUTPUT)–55°C to125°CMIN8129153129153MAX–40°C to85°CMIN9117139117139MAXMHznsnsUNITswitching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, CL = 50 pF (unless otherwise noted) (see Figure 1)PARAMETERfmaxtPLHtPHLCLKCLR or PRECLKCLR or PREQQQ or QQorQQ or QFROM(INPUT)TO(OUTPUT)–55°C to125°CMIN713..33..314.417.114.417.1MAX–40°C to85°CMIN813.74.43.74.413.115.513.115.5MAXMHznsnsUNITswitching characteristics over recommended operating free-air temperature range,VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)PARAMETERfmaxtPLHtPHLCLKCLR or PRECLKCLR or PREQQQ or QQorQQ or QFROM(INPUT)TO(OUTPUT)–55°C to125°CMIN1002.63.12.63.110.312.210.312.2MAX–40°C to85°CMIN1142.73.22.73.29.411.19.411.1MAXMHznsnsUNIToperating characteristics, VCC = 5 V, TA = 25°CPARAMETERCpdPower dissipation capacitanceTYP56UNITpFPOST OFFICE BOX 655303 DALLAS, TEXAS 75265•5元器件交易网www.cecb2b.comSCHS325 – JANUARY 2003CD54AC112, CD74AC112DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPSWITH CLEAR AND PRESETPARAMETER MEASUREMENT INFORMATIONR1 = 500 Ω†S12 × VCCOpenGNDR2 = 500 Ω†TESTtPLH/tPHLtPLZ/tPZLtPHZ/tPZHS1Open2 × VCCGND From OutputUnder TestCL = 50 pF(see Note A)tw†When VCC = 1.5 V, R1 = R2 = 1 kΩLOAD CIRCUITVOLTAGE WAVEFORMSPULSE DURATIONVCC50% VCC0 VtsuData50%Input10%90%trth90%VCC50% VCC10%0 VtfVCCInput50% VCC50% VCC0 VCLRInput50% VCCtrecVCC0 VVCC0 VReferenceInputCLK50% VCCVOLTAGE WAVEFORMSRECOVERY TIMEVOLTAGE WAVEFORMSSETUP AND HOLD AND INPUT RISE AND FALL TIMESVCC0 VOutputControltPZL50% VCCtPZHOutputWaveform 2S1 at GND(see Note B)50% VCC50% VCC50% VCC0 VtPLZ≈VCC20% VCCVOLtPHZVOH80% VCC≈0 VVCCInput50% VCCtPLH50% VCCtPHL90%tr50% VCC10%tf90%In-PhaseOutput50%10%tPHLtPLH50%10%VOH50% VCC10%VOLtfV90%OHtrVOLOutputWaveform 1S1 at 2 × VCC(see Note B)Out-of-PhaseOutput90%VOLTAGE WAVEFORMSPROPAGATION DELAY AND OUTPUT TRANSITION TIMESVOLTAGE WAVEFORMSOUTPUT ENABLE AND DISABLE TIMESNOTES:A.CL includes probe and test-fixture capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.Phase relationships between waveforms are arbitrary.D.For clock inputs, fmax is measured with the input duty cycle at 50%.E.The outputs are measured one at a time with one input transition per measurement.F.tPLH and tPHL are the same as tpd.G.tPZL and tPZH are the same as ten.H.tPLZ and tPHZ are the same as tdis.I.All parameters and waveforms are not applicable to all devices.Figure 1. Load Circuit and Voltage Waveforms6POST OFFICE BOX 655303 DALLAS, TEXAS 75265•元器件交易网www.cecb2b.com
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